Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2003
11/18/2003US6649543 Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices
11/18/2003US6649542 Multi-level type nonvolatile semiconductor memory device
11/18/2003US6649541 Method for preventing or reducing delamination of deposited insulating layers
11/18/2003US6649540 Applying on semiconductor or integrated circuit surface substituted organosilane compound precursor, wherein precursor reacts with and deposits on surface and dielectric film
11/18/2003US6649539 Semiconductor contact fabrication method
11/18/2003US6649538 Method for plasma treating and plasma nitriding gate oxides
11/18/2003US6649537 Intermittent pulsed oxidation process
11/18/2003US6649536 Method for fabricating capacitor of semiconductor device
11/18/2003US6649535 Method for ultra-thin gate oxide growth
11/18/2003US6649534 Methods for processing a coating film and for manufacturing a semiconductor element
11/18/2003US6649533 Method and apparatus for forming an under bump metallurgy layer
11/18/2003US6649532 Methods for etching an organic anti-reflective coating
11/18/2003US6649531 Process for forming a damascene structure
11/18/2003US6649530 Inactive gas is passed in a chamber that is under a reduced pressure; after the chamber is set to a specified pressure, the inactive gas is switched to an active gas and plasma is generated in the active gas; etching of semiconductor wafers
11/18/2003US6649528 Local dry etching method
11/18/2003US6649527 Method of etching a substrate
11/18/2003US6649526 Method for implanting and coding a read-only memory with automatic alignment at four corners
11/18/2003US6649525 Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process
11/18/2003US6649523 Method and system to provide material removal and planarization employing a reactive pad
11/18/2003US6649522 Etch stop in damascene interconnect structure and method of making
11/18/2003US6649520 Method of forming film for reduced ohmic contact resistance and ternary phase layer amorphous diffusion barrier
11/18/2003US6649519 Reducing reflectivity on a semiconductor wafer by annealing titanium and aluminum
11/18/2003US6649518 Method of forming a conductive contact
11/18/2003US6649517 Copper metal structure for the reduction of intra-metal capacitance
11/18/2003US6649515 Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures
11/18/2003US6649514 EEPROM device having improved data retention and process for fabricating the device
11/18/2003US6649513 Copper back-end-of-line by electropolish
11/18/2003US6649512 Method for improving adhesion of a low k dielectric to a barrier layer
11/18/2003US6649510 Method of forming semiconductor memory device using a double layered capping pattern
11/18/2003US6649509 Post passivation metal scheme for high-performance integrated circuit devices
11/18/2003US6649508 Methods of forming self-aligned contact structures in semiconductor integrated circuit devices
11/18/2003US6649507 Dual layer photoresist method for fabricating a mushroom bumping plating structure
11/18/2003US6649506 Method of fabricating vias in solder pads of a ball grid array (BGA) substrate
11/18/2003US6649505 Method for fabricating and identifying integrated circuits and self-identifying integrated circuits
11/18/2003US6649504 Method for fabricating high aspect ratio electrodes
11/18/2003US6649503 Methods of fabricating integrated circuit devices having spin on glass (SOG) insulating layers and integrated circuit devices fabricated thereby
11/18/2003US6649502 Methods of forming multilayer dielectric regions using varied deposition parameters
11/18/2003US6649501 Method for forming a bit line for a semiconductor device
11/18/2003US6649500 Semiconductor device including an insulated gate field effect transistor and method of manufacturing the same
11/18/2003US6649499 Method of varying the resistance along a conductive layer
11/18/2003US6649498 Metal film protection of the surface of a structure formed on a semiconductor substrate during etching of the substrate by a KOH etchant
11/18/2003US6649497 Method of forming vias in silicon carbide and resulting devices and circuits
11/18/2003US6649495 Manufacturing method of semiconductor device
11/18/2003US6649494 Manufacturing method of compound semiconductor wafer
11/18/2003US6649493 Method for fabricating a III nitride film, and underlayer for fabricating a III nitride film and a method for fabricating the same underlayer
11/18/2003US6649492 Strained Si based layer made by UHV-CVD, and devices therein
11/18/2003US6649490 Methods for forming integrated circuit devices through selective etching of an insulation layer to increase the self-aligned contact area adjacent a semiconductor region and integrated circuit devices formed thereby
11/18/2003US6649489 Poly etching solution to improve silicon trench for low STI profile
11/18/2003US6649488 Method of shallow trench isolation
11/18/2003US6649487 Method of manufacturing semiconductor integrated circuit device
11/18/2003US6649486 Method to form shallow trench isolations
11/18/2003US6649485 Method for the formation and lift-off of porous silicon layers
11/18/2003US6649484 Aligning method, exposure apparatus using this aligning method, and semiconductor device manufacturing method utilizing this exposure apparatus
11/18/2003US6649483 Method for fabricating a capacitor configuration
11/18/2003US6649482 Bipolar transistor with a silicon germanium base and an ultra small self-aligned polysilicon emitter and method of forming the transistor
11/18/2003US6649481 Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits
11/18/2003US6649480 Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
11/18/2003US6649479 Method for fabricating MOSFET device
11/18/2003US6649478 Semiconductor device and method of manufacturing same
11/18/2003US6649477 Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
11/18/2003US6649476 Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
11/18/2003US6649475 Method of forming twin-spacer gate flash device and the structure of the same
11/18/2003US6649474 Method for fabricating a source line of a flash memory cell
11/18/2003US6649473 Method of fabricating a floating gate for split gate flash memory
11/18/2003US6649472 Method of manufacturing a flash memory cell with high programming efficiency by coupling from floating gate to sidewall
11/18/2003US6649471 Method of planarizing non-volatile memory device
11/18/2003US6649470 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
11/18/2003US6649469 Methods of forming capacitors
11/18/2003US6649468 Method for fabricating a microelectronic component
11/18/2003US6649467 Method of making high density semiconductor memory
11/18/2003US6649466 Method of forming DRAM circuitry
11/18/2003US6649465 Process for manufacturing a semiconductor memory device including a memory cell selecting transistor and a capacitor with metal electrodes
11/18/2003US6649464 Method for manufacturing semiconductor device having capacitor and via contact
11/18/2003US6649463 Regulating resistor network, semiconductor device including the resistor network, and method for fabricating the device
11/18/2003US6649462 Semiconductor device and method of manufacturing the same including T-shaped gate
11/18/2003US6649461 Method of angle implant to improve transistor reverse narrow width effect
11/18/2003US6649460 Fabricating a substantially self-aligned MOSFET
11/18/2003US6649459 Method for manufacturing a semiconductor component
11/18/2003US6649458 Method for manufacturing semiconductor device with hetero junction bipolar transistor
11/18/2003US6649457 Method for SOI device isolation
11/18/2003US6649456 SRAM cell design for soft error rate immunity
11/18/2003US6649455 SOI type MOS element and manufacturing method thereof
11/18/2003US6649454 Method for fabricating a charge coupled device
11/18/2003US6649453 Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation
11/18/2003US6649452 Method for manufacturing a lithographic reticle for transferring an integrated circuit design to a semiconductor wafer
11/18/2003US6649451 Structure and method for wafer comprising dielectric and semiconductor
11/18/2003US6649450 Method of producing an integrated circuit and an integrated circuit
11/18/2003US6649449 PVD target comprising one or more of Ta, Co, CoTaZr, CoPt, Pt, FeTa, TiZr, CoNb, Mo, CoCrPt, Al, AlCuFe, FeMn or FeAl; bonding layer forming a strong diffusion bond to the target
11/18/2003US6649448 Method of manufacturing a semiconductor device having flexible wiring substrate
11/18/2003US6649447 Methods for plastic injection molding, with particular applicability in facilitating use of high density lead frames
11/18/2003US6649446 Hermetic package for multiple contact-sensitive electronic devices and methods of manufacturing thereof
11/18/2003US6649445 Wafer coating and singulation method
11/18/2003US6649444 Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
11/18/2003US6649439 Semiconductor-air gap grating fabrication using a sacrificial layer process
11/18/2003US6649438 Manufacturing method for two-dimensional image detectors and two-dimensional image detectors
11/18/2003US6649434 Hetero-epitaxially grown at a high temperature of >/= 500 degrees C. and supply of oxygen is stopped and gradual cooling
11/18/2003US6649430 Characteristic evaluation apparatus for insulated gate type transistors
11/18/2003US6649429 In-line electrical monitor for measuring mechanical stress at the device level on a semiconductor wafer
11/18/2003US6649428 Semiconductor chip, semiconductor integrated circuit using the same, and method of selecting semiconductor chip
11/18/2003US6649427 Method for evaluating impurity concentrations in epitaxial susceptors
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