Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2003
11/20/2003WO2003095139A1 Finishing machine using laser beam
11/20/2003WO2003095115A1 Method and device for local treatment of substrates
11/20/2003WO2003095108A1 Method and apparatus for two dimensional assembly of particles
11/20/2003WO2003069286A3 Method and apparatus to measure fiber optic pickup errors in interferometry systems
11/20/2003WO2003067629A3 Band gap compensated hbt
11/20/2003WO2003065411A3 Method of fabricating three-dimensional components using endpoint detection
11/20/2003WO2003064977A3 Multiple degree of freedom interferometer
11/20/2003WO2003058644A3 Superhard dielectric compounds and methods of preparation
11/20/2003WO2003056603A3 Self-ionized and inductively-coupled plasma for sputtering and resputtering
11/20/2003WO2003052815A3 Electrode structure for use in an integrated circuit
11/20/2003WO2003050881A3 Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making same
11/20/2003WO2003041186A3 Organic thin film transistor with siloxane polymer interface
11/20/2003WO2003041124A3 Method of fabricating a gate stack at low temperature
11/20/2003WO2003038863A3 Trench dmos device with improved drain contact
11/20/2003WO2003034491A3 Semiconductor component
11/20/2003WO2003030278A3 Composition, method and electronic device
11/20/2003WO2003028100A3 Encapsulation of pin solder for maintaining accuracy in pin position
11/20/2003WO2003025942A3 Magnetic memory with spin-polarized current writing, using amorphous ferromagnetic alloys, writing method for same
11/20/2003WO2003023825A3 Substrate processing apparatus
11/20/2003WO2003023820A3 Boat for ball attach manufacturing process and method of fabricating reliable flip-chip assembly
11/20/2003WO2003021656A3 Improved material for use with ferroelectrics
11/20/2003WO2003019656A3 Interconnect module with reduced power distribution impedance
11/20/2003WO2003019653A3 Method for producing contacts and printed circuit packages
11/20/2003WO2003019630A3 Unified frame for semiconductor material handling system
11/20/2003WO2003019629A3 Process for charged particle beam micro-machining of copper
11/20/2003WO2003019290A3 Patterning an integrated circuit using a reflective mask
11/20/2003WO2003017724A3 Power and/or energy monitor, method of using, and display device
11/20/2003WO2003017373A3 Piezoelectric coupled component integrated devices
11/20/2003WO2003015132A3 Dual layer hard mask for edram gate etch process
11/20/2003WO2003012850B1 Selective metal oxide removal
11/20/2003WO2003012840A3 Method and device for the production of thin epiatctic semiconductor layers
11/20/2003WO2003009347A3 Integrated system for tool front-end workpiece handling
11/20/2003WO2003009342A3 Data carrier for contactless communication with an integrated component
11/20/2003WO2003007341A3 Tunable radiation source providing a planar irradiation pattern for processing semiconductor wafers
11/20/2003WO2003003458A3 Power pads for application of high current per bond pad in silicon technology
11/20/2003WO2002101817A3 Method and apparatus for controlling a thickness of a copper film
11/20/2003WO2002099853B1 Temperature-controlled chuck and method for controlling the temperature of a substantially flat object
11/20/2003WO2002095819A3 Structure and method to preserve sti during etching
11/20/2003WO2002080240A3 Method for producing a semi-conductor arrangement and the use of an ion beam arrangement for carrying out said method
11/20/2003WO2002078087A3 Semiconductor chip having multiple conductive layers in an opening, and method for fabricating same
11/20/2003WO2002065475A8 Self-aligned conductive line for cross-point magnetic memory integrated circuits
11/20/2003WO2002064853A3 Thin films and methods of making them using trisilane
11/20/2003WO2002057179A3 Fabrication of silicon micro mechanical structures
11/20/2003WO2002043466A9 Non-thermionic sputter material transport device, methods of use, and materials produced thereby
11/20/2003WO2002025719A8 Reduced capacitance scaled hbt using a separate base post layer
11/20/2003US20030217348 Method for designing semiconductor circuit
11/20/2003US20030217347 Method and apparatus for optimizing distributed multiplexed bus interconnects
11/20/2003US20030217344 Design method of semiconductor device
11/20/2003US20030217343 Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing
11/20/2003US20030217342 Circuitry cross-talk analysis with consideration of signal transitions
11/20/2003US20030217317 Method and apparatus for displaying test results and recording medium
11/20/2003US20030216931 Method and system for electronic commerce of semiconductor IP
11/20/2003US20030216827 Synthesizing semiconductor process flow models
11/20/2003US20030216495 Acid generator and thin film composition containing the same
11/20/2003US20030216270 Mixture of an aliphatic polycarboxylic acid and one or two of glyoxylic acid, ascorbic acid, glucose, fructose, lactose, and mannose; pH of less than 3.0.
11/20/2003US20030216269 Cleaning fluid comprising an adduct of hydrogen fluoride with a Lewis base (especially pyridine, polyvinylpyridine or triethylamine) in a carbon dioxide solvent
11/20/2003US20030216112 Cleaning device and method for cleaning polishing cloths used for polishing semiconductor wafers
11/20/2003US20030216108 Polishing pad sensor assembly with a damping pad
11/20/2003US20030216107 Polishing pad with optical sensor
11/20/2003US20030216105 Apparatus for monitoring a metal layer during chemical mechanical polishing using a phase difference signal
11/20/2003US20030216104 Method for processing a work piece in a multi-zonal processing apparatus
11/20/2003US20030216059 Plasma nitridation for reduced leakage gate dielectric layers
11/20/2003US20030216058 Process for preparing insulating material having low dielectric constant
11/20/2003US20030216057 Method integrating polymeric interlayer dielectric in integrated circuits
11/20/2003US20030216056 Hydrogen barrier layer and method for fabricating semiconductor device having the same
11/20/2003US20030216055 Method for manufacturing a semiconductor device
11/20/2003US20030216054 Method of manufacturing semiconductor device
11/20/2003US20030216053 Method and device for processing substrate
11/20/2003US20030216052 Method for fabricating semiconductor device
11/20/2003US20030216051 Method for reducing dimensions between patterns on a photoresist
11/20/2003US20030216050 Method of forming active devices of different gatelengths using lithographic printed gate images of same length
11/20/2003US20030216049 Method and composition for the removal of residual materials during substrate planarization
11/20/2003US20030216048 Method for poly tip shape fabrication and tip shape application
11/20/2003US20030216047 Sacrificial feature for corrosion prevention during CMP
11/20/2003US20030216046 Method and system for reducing wafer edge tungsten residue utilizing a spin etch
11/20/2003US20030216045 Hydrogen bubble reduction on the cathode using double-cell designs
11/20/2003US20030216044 Method for forming bottle trenches
11/20/2003US20030216043 Method for producing a device having a semiconductor layer on a lattice mismatched substrate
11/20/2003US20030216042 CMP slurry for oxide film and method of forming semiconductor device using the same
11/20/2003US20030216041 In-situ thermal chamber cleaning
11/20/2003US20030216040 Method of forming copper wire on semiconductor device
11/20/2003US20030216039 Method for fabricating an under bump metallization structure
11/20/2003US20030216038 Dual metal gate transistors for CMOS process
11/20/2003US20030216037 Method and apparatus for sputter deposition
11/20/2003US20030216036 Method of reducing plasma charging damage during dielectric etch process for dual damascene interconnect structures
11/20/2003US20030216035 Method and apparatus for sputter deposition
11/20/2003US20030216034 Method for etching vias
11/20/2003US20030216033 Method for forming wiring structure
11/20/2003US20030216032 Method for forming MRAM bit having a bottom sense layer utilizing electroless plating
11/20/2003US20030216031 Semiconductor device fabrication method
11/20/2003US20030216030 Method for fabricating contact plug with low contact resistance
11/20/2003US20030216029 Method of selectively alloying interconnect regions by deposition process
11/20/2003US20030216028 Hydrogen barrier layer and method for fabricating semiconductor device having the same
11/20/2003US20030216027 Method of forming insulating layer in semiconductor device
11/20/2003US20030216026 Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC)
11/20/2003US20030216025 Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip
11/20/2003US20030216023 Projected contact structures for engaging bumped semiconductor devices and methods of making the same
11/20/2003US20030216022 Semiconductor device and method of fabricating the same
11/20/2003US20030216021 Method for fabricating semiconductor device
11/20/2003US20030216020 Method for forming multi-layer gate structure
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