| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 08/24/1999 | US5943287 Fault tolerant memory system |
| 08/24/1999 | US5943285 Semiconductor memory device |
| 08/24/1999 | US5943283 Address scrambling in a semiconductor memory |
| 08/24/1999 | US5943273 Semiconductor memory device |
| 08/24/1999 | US5941987 Reference cell for integrated circuit security |
| 08/24/1999 | US5941775 Video game memory cassette apparatus |
| 08/24/1999 | US5941447 Manufacturing method for a processor module with dual-bank SRAM cache having shared capacitors |
| 08/19/1999 | WO1999041751A1 Memory device and method |
| 08/18/1999 | EP0935802A1 Staggered row line firing in a single ras cycle |
| 08/17/1999 | US5940603 Method and apparatus for emulating multi-ported memory circuits |
| 08/17/1999 | US5940345 Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register |
| 08/17/1999 | US5940343 Memory sub-word line driver operated by unboosted voltage |
| 08/17/1999 | US5940342 Multi-bank DRAM suitable for integration with processor on common semiconductor chip |
| 08/17/1999 | US5940341 Semiconductor memory device |
| 08/17/1999 | US5940337 Method and apparatus for controlling memory address hold time |
| 08/17/1999 | US5940334 Memory interface circuit including bypass data forwarding with essentially no delay |
| 08/17/1999 | US5940095 Ink jet print head identification circuit with serial out, dynamic shift registers |
| 08/17/1999 | US5939928 Fast high voltage NMOS pass gate for integrated circuit with high voltage generator |
| 08/12/1999 | WO1999040515A1 Real time dram page boundary adjustment |
| 08/12/1999 | WO1999039909A2 Memory expansion circuit for ink jet print head identification circuit |
| 08/12/1999 | DE19823701A1 Equalization pulse width control circuit for data transmission system |
| 08/11/1999 | EP0935255A2 Flash EEPROM system |
| 08/10/1999 | US5936971 Multi-state flash EEprom system with cache memory |
| 08/10/1999 | US5936911 Static type semiconductor memory device with timer circuit |
| 08/10/1999 | US5936894 Dual level wordline clamp for reduced memory cell current |
| 08/10/1999 | US5936892 Memory cell DC characterization apparatus and method |
| 08/10/1999 | US5936431 Input signal variation detection circuit |
| 08/05/1999 | WO1999039351A1 A voltage regulator and boosting circuit for reading a memory cell at low voltage levels |
| 08/04/1999 | EP0933784A1 High voltage driver circuit for the decoding phase in multilevel non-volatile memory devices. |
| 08/04/1999 | EP0933781A2 Integrated circuit |
| 08/04/1999 | CN1044526C Semiconductor memory device |
| 08/03/1999 | US5933855 Shared, reconfigurable memory architectures for digital signal processing |
| 08/03/1999 | US5933388 Sub row decoder circuit for semiconductor memory device |
| 08/03/1999 | US5933387 Divided word line architecture for embedded memories using multiple metal layers |
| 08/03/1999 | US5933050 Semiconductor circuit |
| 07/29/1999 | WO1999027499A3 Secure memory having anti-wire tapping |
| 07/28/1999 | CN1044420C Nonvolatile semiconductor integrated circuit having address transition detector |
| 07/27/1999 | US5930502 Method for sharing a random-access memory between two asynchronous processors and electronic circuit for the implementation of this method |
| 07/27/1999 | US5930196 Multi-bank memory device with compensation for line loading |
| 07/27/1999 | US5930195 Semiconductor memory device |
| 07/27/1999 | US5930162 Quantum random address memory with polymer mixer and/or memory |
| 07/27/1999 | US5929694 Semiconductor device having voltage generation circuit |
| 07/27/1999 | US5929681 Delay circuit applied to semiconductor memory device having auto power-down function |
| 07/27/1999 | US5929539 Semiconductor memory device adaptable to external power supplies of different voltage levels |
| 07/27/1999 | US5929492 Contact structure of column gate and data line |
| 07/27/1999 | US5928361 Data security device and method thereof |
| 07/27/1999 | US5928343 Method for assigning identification values to memories |
| 07/21/1999 | EP0929939A1 Self-timed pulse control circuit |
| 07/21/1999 | EP0929901A1 Memory array, memory cell, and sense amplifier test and characterization |
| 07/21/1999 | EP0929900A1 Data retention test for static memory cell |
| 07/21/1999 | EP0929898A1 Memory block select using multiple word lines to address a single memory cell row |
| 07/21/1999 | EP0929897A1 Dram |
| 07/21/1999 | EP0929896A1 Memory including resistor bit-line loads |
| 07/21/1999 | EP0929895A1 Active power supply filter |
| 07/21/1999 | EP0832486A4 Nonvolatile memory blocking architecture and redundancy |
| 07/20/1999 | US5926827 High density SIMM or DIMM with RAS address re-mapping |
| 07/20/1999 | US5926436 Semiconductor memory device |
| 07/20/1999 | US5926433 Dual strobed negative pumped worldlines for dynamic random access memories |
| 07/20/1999 | US5926432 Semiconductor storage device having a hierarchical bit line structure |
| 07/20/1999 | US5926051 Self refresh timer |
| 07/20/1999 | US5926036 Programmable logic array circuits comprising look up table implementation of fast carry adders and counters |
| 07/15/1999 | WO1999035649A1 A memory supporting multiple address protocols |
| 07/14/1999 | EP0728359A4 Flash eprom integrated circuit architecture |
| 07/14/1999 | CN1222738A Semiconductor memory device having plurality of banks |
| 07/14/1999 | CN1222709A Storage and reproduction apparatus |
| 07/13/1999 | US5923614 Structure and method for reading blocks of data from selectable points in a memory device |
| 07/13/1999 | US5923609 Strobed wordline driver for fast memories |
| 07/13/1999 | US5923608 Scalable N-port memory structures |
| 07/13/1999 | US5923607 Apparatus and method for enlarging metal line pitch of semiconductor memory device |
| 07/13/1999 | US5923605 Space-efficient semiconductor memory having hierarchical column select line architecture |
| 07/13/1999 | US5923604 Method and apparatus for anticipatory selection of external or internal addresses in a synchronous memory device |
| 07/13/1999 | US5923601 In an integrated circuit |
| 07/13/1999 | US5923597 Dynamically variable digital delay line |
| 07/13/1999 | US5923596 Precharge-enable self boosting word line driver for an embedded DRAM |
| 07/13/1999 | US5923593 Multi-port DRAM cell and memory system using same |
| 07/07/1999 | EP0928003A2 Row decoder circuit for an electronic memory device, particularly for low voltage application |
| 07/07/1999 | EP0928002A1 Dual memory for digital signal processor |
| 07/06/1999 | US5920883 Memory device using block write mode, simultaneous column writes with column address selection circuit and segment start/stop address latches |
| 07/06/1999 | US5920517 Memory array test and characterization using isolated memory cell power supply |
| 07/06/1999 | US5920510 Semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor device |
| 07/06/1999 | US5920096 Electrostatic discharge protection systems and methods for electronic tokens |
| 06/30/1999 | EP0926684A1 Synchronisation device for synchronous dynamic random-access memory |
| 06/30/1999 | EP0926683A2 Semiconductor memory |
| 06/30/1999 | EP0926682A2 Multiple bank memory |
| 06/30/1999 | EP0926601A1 Data protection method for a semiconductor memory and corresponding protected memory device |
| 06/30/1999 | CN1221191A Synchronization device for synchronous dynamic random-access memory |
| 06/29/1999 | USRE36236 Semiconductor memory device |
| 06/29/1999 | US5917770 Semiconductor memory device for temporarily storing digital image data |
| 06/29/1999 | US5917769 Method and system rotating data in a memory array device |
| 06/29/1999 | US5917762 Method for delaying a signal |
| 06/29/1999 | US5917757 Flash memory with high speed erasing structure using thin oxide semiconductor devices |
| 06/24/1999 | WO1999031668A1 Reprogrammable memory device with variable page size |
| 06/24/1999 | WO1999031665A1 Memory addressing |
| 06/23/1999 | EP0924765A2 Memory with word line voltage control |
| 06/23/1999 | EP0924685A1 Method of storing data having different formats in a memory and appropriate memory sytem |
| 06/23/1999 | CN1220466A Semiconductor memory having hierarchical bit line and/or word line architecture |
| 06/23/1999 | CN1220465A Memory with word line voltage control |
| 06/22/1999 | US5915105 Memory device |
| 06/22/1999 | US5915084 Scannable sense amplifier circuit |
| 06/22/1999 | US5914910 Semiconductor memory and method of using the same column decoder and image processor |