Patents
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
10/1999
10/19/1999US5970020 Controlling the set up of a memory address
10/19/1999US5970019 Semiconductor memory device with row access in selected column block
10/19/1999US5970018 Semiconductor integrated circuit and decode circuit for memory
10/19/1999US5970017 Decode circuit for use in semiconductor memory device
10/19/1999US5970016 Dynamic semiconductor memory device with banks capable of operating independently
10/19/1999US5970014 Semiconductor memory device having two or more memory blocks
10/19/1999US5970006 Semiconductor memory device having cell array divided into a plurality of cell blocks
10/19/1999US5969977 Electronic memory device having bit lines with block selector switches
10/12/1999US5966731 Protocol for communication with dynamic memory
10/12/1999US5966723 Serial programming mode for non-volatile memory
10/12/1999US5966343 Variable latency memory circuit
10/12/1999US5966340 Semiconductor memory device having hierarchical word line structure
10/12/1999US5966336 Semiconductor device having redundancy circuit
10/12/1999US5966334 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
10/12/1999US5966317 Memory cell
10/12/1999US5964884 Self-timed pulse control circuit
10/12/1999CA2155791C Video memory arrangement
10/06/1999EP0947991A2 Improved dynamic random assess memory circuit and methods therefor
10/06/1999EP0946943A1 Memory and method for sensing sub-groups of memory elements
10/06/1999EP0698272B1 Row decoder and driver with switched-bias bulk regions
10/05/1999US5963505 Sequential access memory with low consumption
10/05/1999US5963500 Semiconductor memory device
10/05/1999US5963492 For use in a memory chip
10/05/1999US5963475 Advanced nonvolatile memories adaptable to dynamic random access memories and methods of operating therein
10/05/1999US5963468 Low latency memories and systems using the same
09/1999
09/30/1999DE19911101A1 Nonvolatile semiconductor memory, such as flash EEPROM
09/29/1999EP0944906A1 Non-volatile memory array that enables simultaneous read and write operations
09/29/1999CN1229996A Non-volatile semiconductor memory device
09/29/1999CN1229992A Memory address generator circuit and semiconductor memory device
09/28/1999USRE36319 Structure for deselective broken select lines in memory arrays
09/28/1999US5959937 Dual clocking scheme in a multi-port RAM
09/28/1999US5959935 Synchronization signal generation circuit and method
09/28/1999US5959934 Pulse wordline control circuit and method for a computer memory device
09/28/1999US5959932 Method and apparatus for detecting errors in the writing of data to a memory
09/28/1999US5959931 Memory system having multiple reading and writing ports
09/28/1999US5959930 Multi-bank synchronous semiconductor memory device
09/28/1999US5959929 Method for writing to multiple banks of a memory device
09/28/1999US5959927 Semiconductor integrated circuit device having hierarchical power source arrangement
09/28/1999US5959925 DRAM incorporating self refresh control circuit and system LSI including the DRAM
09/28/1999US5959907 Semiconductor memory device having a redundancy circuit
09/28/1999US5959902 Voltage level shifter device, particulary for a nonvolatile memory
09/28/1999US5959897 System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers
09/28/1999US5959890 Non-volatile semiconductor memory device
09/28/1999US5959854 Voltage step-up circuit and method for controlling the same
09/28/1999US5959486 Address transition detection circuit
09/28/1999US5959467 High speed dynamic differential logic circuit employing capacitance matching devices
09/23/1999WO1999048101A1 Embedded static random access memory for field programmable gate array
09/23/1999DE19845295A1 Access method for flash memory field improved to enable faster data processing by reducing the table searching time
09/23/1999DE19833570A1 Multi-port semiconductor memory with grouped bitlines
09/22/1999EP0943177A1 Clock vernier adjustment
09/22/1999EP0943146A1 Bi-directional shift register
09/22/1999CN1229249A Semiconductor memory device having means for outputting redundancy replacement selection signal
09/21/1999US5956289 Clock signal from an adjustable oscillator for an integrated circuit
09/21/1999US5956288 Modular memory system with shared memory access
09/21/1999US5956287 Semiconductor memory
09/21/1999US5956286 Data processing system and method for implementing a multi-port memory cell
09/21/1999US5956285 Synchronous semiconductor memory device with multi-bank configuration
09/21/1999US5954804 Synchronous memory device having an internal register
09/16/1999DE19841005A1 Semiconductor disc memory for information processing device
09/15/1999EP0848851B1 Segmented read line circuit particularly useful for multi-port storage arrays
09/15/1999CN1228598A Memory readout circuit and static random access memory
09/14/1999US5953685 Method and apparatus to control core logic temperature
09/14/1999US5953285 Scan path circuitry including an output register having a flow through mode
09/14/1999US5953283 Multi-port SRAM with reduced access requirements
09/14/1999US5953282 Circuit for generating switching control signal
09/14/1999US5953280 Bank selection for synchronous readable and writable semiconductor memory
09/14/1999US5953266 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
09/14/1999US5953259 Integrated circuit memory devices having cross-coupled isolation gate controllers which provide simultaneous reading and writing capability to multiple memory arrays
09/14/1999US5953247 Semiconductor device
09/14/1999US5953242 System with meshed power and signal buses on cell array
09/14/1999US5952868 Voltage level interface circuit with set-up and hold control
09/09/1999DE19909092A1 Semiconductor memory with low energy requirement
09/08/1999EP0940817A2 Improved dynamic access memory delay circuits and methods therefor
09/07/1999US5950220 Method and apparatus for providing a logical double sided memory element by mapping single sided memory elements onto a logical double sided memory address space
09/07/1999US5949737 Address processing circuit
09/07/1999US5949736 Memory control circuit reducing a consumed power of memory
09/07/1999US5949735 Row decoder for semiconductor memory device
09/07/1999US5949734 Semiconductor memory device
09/07/1999US5949719 Field programmable memory array
09/07/1999US5949713 Nonvolatile memory device having sectors of selectable size and number
09/07/1999US5949706 Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line
09/07/1999US5949699 Semiconductor integrated circuit device
09/07/1999US5949698 Semiconductor memory device
09/07/1999US5949697 Semiconductor memory device having hierarchical input/output line structure and method for arranging the same
09/02/1999DE19808347A1 Integrated memory
09/01/1999EP0939444A2 Access structure for high density read only memory
09/01/1999EP0784852A4 High speed, low voltage non-volatile memory
08/1999
08/31/1999US5946269 Synchronous RAM controlling device and method
08/31/1999US5946263 Memory device having separate driver sections
08/31/1999US5946262 RAM having multiple ports sharing common memory locations
08/31/1999US5946261 Dual-port memory
08/31/1999US5946243 Integrated circuit
08/31/1999US5944837 Operation control apparatus
08/25/1999EP0938097A2 Memory reading circuit and SRAM
08/25/1999EP0938095A1 Programmable non-volatile memory and programming method thereof
08/25/1999EP0618535B1 EEPROM card with defective cell substitution and cache memory
08/24/1999US5943292 Address counter circuit and semiconductor memory device
08/24/1999US5943291 Method and apparatus for signal transition detection in integrated circuits
08/24/1999US5943289 Hierarchical word line structure
08/24/1999US5943288 Apparatus and method for minimizing address hold time in asynchronous SRAM