| Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368) |
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| 06/22/1999 | US5914909 Semiconductor memory device capable of driving the data bus sense amplifier in both read and write modes |
| 06/22/1999 | US5914908 Method of operating a boosted wordline |
| 06/22/1999 | US5914906 Field programmable memory array |
| 06/22/1999 | US5914905 Semiconductor integrated circuit |
| 06/16/1999 | EP0839375B1 Pipelined address memory system and method of operating such system |
| 06/16/1999 | EP0819341B1 Multiport ram for use within a viterbi decoder |
| 06/16/1999 | CN1043696C Memory array device |
| 06/15/1999 | USRE36229 Simulcast standard multichip memory addressing system |
| 06/15/1999 | US5913046 Method for performing data transfer operations |
| 06/15/1999 | US5912861 ROM/RAM overlap circuit |
| 06/15/1999 | US5912860 For an array of memory cells |
| 06/15/1999 | US5912857 Row decoder for semiconductor memory device |
| 06/15/1999 | US5912856 Internal voltage generating circuit in semiconductor memory device |
| 06/15/1999 | US5912855 Power up initialization circuit responding to an input signal |
| 06/15/1999 | US5912850 Multi-port RAM with shadow write test enhancement |
| 06/15/1999 | US5912571 Using the internal supply voltage ramp rate to prevent premature enabling of a device during power-up |
| 06/15/1999 | US5912565 In a memory device |
| 06/10/1999 | WO1999028913A1 A method and apparatus for dynamically placing portions of a memory in a reduced power consumption state |
| 06/08/1999 | US5910927 Memory device and sense amplifier control device |
| 06/08/1999 | US5910917 Multi-chip IC memory device with a single command controller and signal clock generator |
| 06/08/1999 | US5910913 Non-volatile semiconductor memory |
| 06/08/1999 | US5910794 Method and apparatus for storing and rotating bit patterns |
| 06/03/1999 | WO1999027499A2 Secure memory having anti-wire tapping |
| 06/03/1999 | WO1999027429A1 A method and apparatus to control core logic temperature |
| 06/03/1999 | CA2311514A1 Secure memory having anti-wire tapping |
| 06/02/1999 | EP0920024A2 Semiconductor memory device having a plurality of banks |
| 06/02/1999 | EP0823117A4 Nonvolatile memory blocking architecture |
| 06/01/1999 | US5909704 High speed address generator |
| 06/01/1999 | US5909407 Word line multi-selection circuit for a memory device |
| 06/01/1999 | US5909396 High voltage NMOS pass gate having supply range, area, and speed advantages |
| 06/01/1999 | US5909388 Dynamic random access memory circuit and methods therefor |
| 06/01/1999 | US5909247 Solid-state image pickup apparatus |
| 06/01/1999 | US5909141 Step-up potential supply circuit and semiconductor storage device |
| 05/27/1999 | WO1999026253A1 Programmable access protection in a flash memory device |
| 05/27/1999 | DE19751737A1 Memory chip operating method for repeated programming of e.g. EEPROM, FLASH memory |
| 05/27/1999 | CA2310080A1 Programmable access protection in a flash memory device |
| 05/26/1999 | EP0918336A1 Electrically programmable and erasable non volatile memory with read- and/or write protection and incorporated electronical system |
| 05/26/1999 | CN1217546A Synchronous semiconductor storage device having timed circuit of controlling activation/non-activation of word line |
| 05/26/1999 | CN1217544A Semiconductor device and drive method therefor |
| 05/25/1999 | US5907861 Destructive read protection using address blocking technique |
| 05/25/1999 | US5907856 Moving sectors within a block of information in a flash memory mass storage architecture |
| 05/25/1999 | US5907700 Controlling flash memory program and erase pulses |
| 05/25/1999 | US5907520 Equalization pulse generating circuit for memory device |
| 05/25/1999 | US5907517 Memory circuit yield generator and timing adjustor |
| 05/25/1999 | US5907508 Method and apparatus for single clocked, non-overlapping access in a multi-port memory cell |
| 05/20/1999 | WO1999010892B1 Low voltage and low power static random access memory (sram) |
| 05/19/1999 | EP0917153A1 Semiconductor memory device |
| 05/19/1999 | EP0806045A4 Decoded wordline driver with positive and negative voltage modes |
| 05/18/1999 | US5905689 Column decoder array device |
| 05/18/1999 | US5905683 Method and structure for recovering smaller density memories from larger density memories |
| 05/18/1999 | US5905673 Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
| 05/18/1999 | US5905400 Circuit configuration for generating a boosted output voltage |
| 05/18/1999 | CA2127947C Fully scalable memory apparatus |
| 05/12/1999 | EP0915478A1 Improved boosting circuit, particularly for a memory device |
| 05/12/1999 | EP0915477A1 Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory |
| 05/12/1999 | EP0915476A1 Method and circuit for regulating the length of an ATD pulse signal |
| 05/12/1999 | EP0915421A2 Semiconductor memory device capable of preventing malfunction due to disconnection of column select line or word select line |
| 05/11/1999 | US5903514 Multi-bank synchronous semiconductor memory device |
| 05/11/1999 | US5903511 Flexible DRAM array |
| 05/11/1999 | US5903510 Address decoder, semiconductor memory and semiconductor device |
| 05/11/1999 | US5903488 Semiconductor memory with improved word line structure |
| 05/11/1999 | US5903022 Semiconductor memory device having improved word line arrangement in a memory cell array |
| 05/06/1999 | WO1999022376A1 High speed memory self-timing circuitry and methods for implementing the same |
| 05/06/1999 | EP0913829A1 Memory circuit with improved address signal generator |
| 05/06/1999 | DE19837016A1 Integrated semiconductor device with multi-bank memory for e.g. microprocessor |
| 05/05/1999 | CN1215893A Space-efficient semiconductor memory having hierarchical column select line architecture |
| 05/04/1999 | US5901304 Emulating quasi-synchronous DRAM with asynchronous DRAM |
| 05/04/1999 | US5901111 Enhanced multiple block writes to adjacent block of memory using a sequential counter |
| 05/04/1999 | US5901109 Semiconductor memory device capable of higher-speed operation and activated in synchronism with clock |
| 05/04/1999 | US5901107 Semiconductor memory device selection method and circuit for embodying the same |
| 05/04/1999 | US5901104 Data processing device |
| 05/04/1999 | US5901103 Integrated circuit having standby control for memory and method thereof |
| 05/04/1999 | US5901102 Semiconductor memory device achieving reduction in access time without increase in power consumption |
| 05/04/1999 | US5901092 Memory device having pipelined access and method for pipelining data access |
| 05/04/1999 | US5901081 Circuit and method for preconditioning memory word lines across word line boundaries |
| 05/04/1999 | US5901079 Skewed memory cell apparatus and method |
| 04/29/1999 | DE19849339A1 Word conductor driver for semiconductor memory |
| 04/28/1999 | EP0829087B1 Process for the selective programming of a non-volatile store |
| 04/27/1999 | US5898641 Address transition circuit for a memory |
| 04/27/1999 | US5898638 Latching wordline driver for multi-bank memory |
| 04/27/1999 | US5898637 System and method for selecting shorted wordlines of an array having dual wordline drivers |
| 04/27/1999 | US5898619 Memory cell having a plural transistor transmission gate and method of formation |
| 04/27/1999 | US5897668 Memory system for storing information data and state-of-radio-transmission data |
| 04/27/1999 | US5897659 Modifying RAS timing based on wait states to accommodate different speed grade DRAMs |
| 04/22/1999 | WO1999019879A1 Dram core refresh with reduced spike current |
| 04/21/1999 | CN1214794A Semiconductor memory device |
| 04/21/1999 | CN1214793A Semiconductor memory device |
| 04/21/1999 | CN1214516A Semiconductor integrated circuit device |
| 04/20/1999 | US5896345 Row decoder for a semiconductor memory device |
| 04/20/1999 | US5896344 Local word line decoder for memory with 2 1/2 MOS devices |
| 04/20/1999 | US5896343 Semiconductor memory device having additional driver circuit for reducing signal propagation delay |
| 04/20/1999 | US5896341 Synchronous semiconductor memory circuit |
| 04/20/1999 | US5896340 Multiple array architecture for analog or multi-bit-cell memory |
| 04/20/1999 | US5896330 Multi-port random access memory with shadow write test mode |
| 04/20/1999 | US5896322 Multiple-port ring buffer |
| 04/20/1999 | US5896310 Multiple bank memory with over-the-array conductors programmable for providing either column factor or y-decoder power connectivity |
| 04/20/1999 | US5896052 Methods to avoid instability |
| 04/20/1999 | US5895481 Programmable VESA unified memory architecture (VUMA) row address strobe (RAS) |
| 04/15/1999 | WO1998043176A8 Shared reconfigurable memory architectures for digital signal processing |
| 04/14/1999 | EP0908892A2 Semiconductor integrated circuit device |