| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 06/05/2001 | US6243808 Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups |
| 06/05/2001 | US6243799 Methods and apparatus for byte alignment operations for a memory device that stores an odd number of bytes |
| 06/05/2001 | US6243769 Dynamic buffer allocation for a computer system |
| 06/05/2001 | US6243728 Partitioned shift right logic circuit having rounding support |
| 06/05/2001 | US6243081 Data structure for efficient retrieval of compressed texture data from a memory system |
| 05/31/2001 | DE19956083A1 Buffer read-out clock adjusting method for serial data transmission system |
| 05/30/2001 | EP1103969A2 Optical disc buffer under-run handling method |
| 05/30/2001 | CN1297615A Processor and processing method |
| 05/29/2001 | US6240031 Memory architecture |
| 05/29/2001 | US6239631 Integrated circuit device with input buffer capable of correspondence with highspeed clock |
| 05/25/2001 | WO2001037076A2 Method and apparatus for ring buffer flow error detection |
| 05/23/2001 | EP1102160A2 Synchronous digital data transmitter |
| 05/22/2001 | US6237080 Executable programs |
| 05/16/2001 | EP1099153A1 Storage device and a method for operating the storage device |
| 05/16/2001 | CN1295685A Interface apparatus for connecting devices operating at different clock rates, and method of operating interface |
| 05/15/2001 | US6233707 Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clock |
| 05/15/2001 | US6233674 Method and system for scope-based compression of register and literal encoding in a reduced instruction set computer (RISC) |
| 05/15/2001 | US6233651 Programmable FIFO memory scheme |
| 05/15/2001 | US6233642 Method of wiring a 64-bit rotator to minimize area and maximize performance |
| 05/15/2001 | US6233629 Self-adjusting elasticity data buffer with preload value |
| 05/15/2001 | US6233252 Transfer of very large digital data files via a fragmentation and reassembly methodology |
| 05/15/2001 | US6233244 Method and apparatus for reclaiming buffers |
| 05/15/2001 | US6233191 Field programmable memory array |
| 05/10/2001 | WO2001033716A1 Gray-code counter having a binary incrementer and method of operating the same |
| 05/09/2001 | EP1098314A1 Method and apparatus for decoding |
| 05/08/2001 | US6230249 Methods and apparatus for providing logical cell available information in a memory |
| 05/08/2001 | US6230191 Method and apparatus for regulating the amount of buffer memory requested by a port in a multi-port switching device with shared buffer memory |
| 05/08/2001 | US6230163 Transient datastream-processing buffer memory organization with software management adapted for multilevel housekeeping |
| 05/08/2001 | US6229459 Data converting method and apparatus therefor |
| 05/03/2001 | WO2000073872A3 Fft processor with overflow prevention |
| 05/02/2001 | EP1096506A1 Shift register allowing direct data insertion |
| 05/02/2001 | EP1095821A2 Apparatus and method for data width reduction in automotive systems |
| 05/01/2001 | US6226698 Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO |
| 05/01/2001 | US6226680 Intelligent network interface system method for protocol processing |
| 05/01/2001 | US6226338 Multiple channel data communication buffer with single transmit and receive memories |
| 04/26/2001 | WO2001029650A1 Multiple time domain serial-to-parallel converter |
| 04/25/2001 | EP1094637A2 IEEE 1394 bus interface |
| 04/25/2001 | EP1093607A1 Fifo system with variable-width interface to host processor |
| 04/24/2001 | US6223261 Communication system method and recording apparatus for performing arbitrary application processing |
| 04/18/2001 | EP1093232A1 Processor and processing method |
| 04/17/2001 | US6219738 Information processing system |
| 04/17/2001 | US6218860 Programmable logic array integrated circuit incorporating a first-in first-out memory |
| 04/11/2001 | EP1091289A1 Device for processing sonet or SDH frames-DS0 to channel mapping |
| 04/11/2001 | EP1091288A1 Device for processing sonet or SDH frames having an H.100 bus |
| 04/11/2001 | CN1064499C Method for controlling access to a buffer, apparatus for temporarily storing data packets and exchange device |
| 04/10/2001 | US6216205 Methods of controlling memory buffers having tri-port cache arrays therein |
| 04/10/2001 | US6216182 Method and apparatus for serving data with adaptable interrupts |
| 04/10/2001 | US6215906 Data compression and restoration system for encoding an input character on the basis of a conditional appearance rate obtained in relation to an immediately preceding character string |
| 04/10/2001 | CA2105866C Method and apparatus for buffering data within stations of a communication network |
| 04/04/2001 | EP1089518A2 Decompressing data |
| 04/04/2001 | EP1089166A2 An integer instruction set architecture and implementation |
| 04/03/2001 | US6212122 Dual port memory operation method with synchronized read and write pointers |
| 04/03/2001 | US6211802 Semiconductor integrated circuit for performing data transfer |
| 03/28/2001 | EP1086416A1 An interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface |
| 03/28/2001 | CN1289096A Data conversion system |
| 03/27/2001 | US6209047 RAM data transmitting apparatus and method using a FIFO memory with three fullness flags |
| 03/27/2001 | US6209012 System and method using mode bits to support multiple coding standards |
| 03/27/2001 | US6208703 First-in-first-out synchronizer |
| 03/27/2001 | US6208566 Semiconductor integrated circuit |
| 03/21/2001 | EP1085428A2 Data conversion system |
| 03/20/2001 | US6205511 SDRAM address translator |
| 03/13/2001 | US6202164 Data rate synchronization by frame rate adjustment |
| 03/13/2001 | US6201845 Data processing apparatus adapted for data transfer between circuit units operating with different clock cycles |
| 03/08/2001 | WO2001016757A1 A system and method for streaming data in java |
| 03/07/2001 | EP1080433A1 Circuit and method for calibrating phase shift between a plurality of digitizers in a data acquisition system |
| 03/07/2001 | EP1080432A1 Data acquisition system comprising means for analysing and storing in real time |
| 03/07/2001 | EP1080431A1 Ques |
| 02/28/2001 | EP1079329A2 Adaptive image coding |
| 02/27/2001 | US6195743 Method and system for compressing reduced instruction set computer (RISC) executable code through instruction set expansion |
| 02/27/2001 | US6195672 Saturation detection in floating point to integer conversions |
| 02/27/2001 | US6195466 Reversible DCT for lossless-lossy compression |
| 02/21/2001 | EP1076856A1 Cache memory for two-dimensional data fields |
| 02/20/2001 | US6192428 Method/apparatus for dynamically changing FIFO draining priority through asynchronous or isochronous DMA engines in response to packet type and predetermined high watermark being reached |
| 02/20/2001 | US6191993 First in first out memory circuit |
| 02/20/2001 | US6191992 First-in-first-out storage device including synchronized full-state detention and empty-state detention |
| 02/20/2001 | US6191991 Data rate converter |
| 02/13/2001 | US6189054 System for operating a circulating memory which can be addressed via a write and/or read pointer by outputting a signal upon an occurrence of a jump of the pointer |
| 02/08/2001 | WO2001009712A1 Processor with improved accuracy for multiply-add operations |
| 02/08/2001 | WO2001009710A1 Method and device for writing and reading a buffer memory |
| 02/07/2001 | EP1074967A1 Image signal processing device |
| 02/07/2001 | EP1073950A1 Method and apparatus for performing shift operations on packed data |
| 02/06/2001 | US6185641 Dynamically allocating space in RAM shared between multiple USB endpoints and USB host |
| 02/06/2001 | US6185593 Method and apparatus for parallel normalization and rounding technique for floating point arithmetic operations |
| 01/30/2001 | US6181596 Method and apparatus for a RAM circuit having N-Nary output interface |
| 01/25/2001 | WO2001006347A1 Stack of operands and method for stacking of operands |
| 01/25/2001 | DE19933130A1 Operandenstapelspeicher und Verfahren zum Betreiben eines Operandenstapelspeichers An operand stack and method of operating an operand stack |
| 01/24/2001 | EP1071005A2 Data transfer apparatus for system having plural clock domains |
| 01/24/2001 | CN1281559A Method of emulating shift register using RAM |
| 01/24/2001 | CN1281306A Data transmission device used in system possessing multiple clock ranges |
| 01/23/2001 | US6178473 System for selectively incrementing a count number of an associated node only when the node is put in use in conjunction with a successful compare and swap operation |
| 01/23/2001 | US6178436 Apparatus and method for multiplication in large finite fields |
| 01/18/2001 | WO2001004724A2 A partitioned shift right logic circuit having rounding support |
| 01/18/2001 | DE10001168A1 Output-first-in-first-out (OFIFO)-data transmission control device, has write-read cursor generator for providing a cursor for identifying location of instructed stored data |
| 01/17/2001 | EP1068569A1 Device and method for buffer protection |
| 01/16/2001 | US6175847 Shifting for parallel normalization and rounding technique for floating point arithmetic operations |
| 01/11/2001 | DE10024640A1 Delay-signal generation device for semiconductor device testing apparatus, chooses a suitable signal from phase shifter, which is phase shifted by predefined amount from reference, and outputs it as delay signal |
| 01/09/2001 | US6173307 Multiple-reader multiple-writer queue for a computer system |
| 01/09/2001 | US6173299 Method and apparatus for selecting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations |
| 01/09/2001 | US6173084 Noise reduction in an image |
| 01/09/2001 | US6172964 Clock synchronization |