Patents
Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
08/2003
08/20/2003EP0960536B1 Queuing structure and method for prioritization of frames in a network switch
08/14/2003WO2002050656A3 Apparatus and method for generating fifo fullness indicator signals
08/14/2003US20030154360 Methods of performing DSP operations using flexible data type operands
08/12/2003US6606674 Method and apparatus for reducing circular list's thrashing by detecting the queues' status on a circular linked list
08/06/2003EP1190324B1 Process for the secure writing of a pointer for a circular memory
08/06/2003CN1117379C Field programmable memory array
08/06/2003CN1116989C Tape printers
08/05/2003US6604179 Reading a FIFO in dual clock domains
08/05/2003US6604169 Modulo addressing based on absolute offset
08/05/2003US6603336 Signal duration representation by conformational clock cycles in different time domains
07/2003
07/31/2003WO2002077829A3 A communication system
07/31/2003US20030141898 Programmable logic devices with function-specific blocks
07/31/2003US20030141897 Multi-access FIFO queue
07/30/2003EP1330700A1 Multiplier and shift device using signed digit representation
07/30/2003EP1252564B1 Method and apparatus for increasing the battery life of portable electronic devices
07/24/2003WO2003060692A2 Shifting device and shifting method
07/24/2003US20030138159 Data compression
07/24/2003US20030137880 Buffer memory device
07/23/2003CN1432156A Data processing system and data processing method
07/23/2003CN1431588A Logic reorganizable circuit
07/23/2003CN1431580A Command source operated on packed datas
07/23/2003CN1431579A Super-speed type method for displaying character string
07/22/2003US6598151 Stack Pointer Management
07/22/2003US6597707 Circuitry, architecture and methods for synchronizing data
07/17/2003WO2003058425A1 System and method to remotely manage and audit set top box resources
07/16/2003CN1114951C Semiconductor integrated circuit of reducing power consuming
07/16/2003CN1114912C Recording and reproducing system for simultaneous recording and reproduction via information
07/15/2003US6594815 Asynchronous controller generation method
07/15/2003US6594714 Reconfigurable FIFO interface to support multiple channels in bundled agent configurations
07/15/2003US6594325 Circuitry, architecture and method(s) for synchronizing data
07/10/2003US20030131216 Apparatus for one-cycle decompression of compressed data and methods of operation thereof
07/10/2003US20030131162 Non-destructive read FIFO
07/10/2003US20030131029 Barrel shifter
07/10/2003US20030128799 Calculating circuit for dividing a fixed-point signal
07/10/2003US20030128611 Multiple mode elastic data transfer interface
07/10/2003US20030127996 Intelligent electrical switching device
07/09/2003CN1428983A Equipment for data transmission between transmission systems using difference phase clock and its method
07/03/2003US20030126491 Universal asynchronous boundary module
07/03/2003US20030126341 Method and apparatus for eliminating the software generated ready-signal to hardware devices that are not part of the memory coherency domain
07/03/2003US20030123588 Synchronizing data or signal transfer across clocked logic domains
07/02/2003EP1323026A1 Method and apparatus for flexible data types
07/02/2003EP1076856B1 Cache memory for two-dimensional data fields
07/01/2003US6587864 Galois field linear transformer
06/2003
06/26/2003US20030120886 Method and apparatus for buffer partitioning without loss of data
06/26/2003US20030120884 Memory system for increased bandwidth
06/26/2003US20030120879 Methods and apparatus for forming linked list queue using chunk-based structure
06/26/2003US20030120842 Writing and reading data from a queue
06/26/2003US20030120664 Method and apparatus for reassembly of data blocks within a network processor
06/26/2003US20030118140 Apparatus and method for transmitting data between transmission systems using dissimilar phase clocks
06/25/2003EP1321863A2 Methods and apparatus for forming linked list queue using chunk-based structure
06/24/2003US6584584 Method and apparatus for detecting errors in a First-In-First-Out buffer
06/24/2003US6584537 Data-cache data-path
06/24/2003US6584529 Intermediate buffer control for improving throughput of split transaction interconnect
06/19/2003US20030112685 FIFO memory devices having single data rate (SDR) and dual data rate (DDR) capability
06/19/2003US20030112051 Data transfer circuit between different clock regions
06/18/2003CN1425152A Method and apparatus for increasing battery life of portable electronic devices
06/17/2003US6581165 System for asynchronously transferring timed data using first and second clock signals for reading and writing respectively when both clock signals maintaining predetermined phase offset
06/17/2003US6581164 System for adjusting clock frequency based upon amount of unread data stored in sequential memory when reading a new line of data within a field of data
06/17/2003US6581147 Data flow control circuitry including buffer circuitry that stores data access requests and data
06/17/2003US6581144 Method and logic for initializing the forward-pointer memory during normal operation of the device as a background process
06/17/2003US6581087 Floating point adder capable of rapid clip-code generation
06/17/2003US6581063 Method and apparatus for maintaining a linked list
06/12/2003WO2003048924A1 Galois field linear transformer
06/10/2003US6578118 Method and logic for storing and extracting in-band multicast port information stored along with the data in a single memory without memory read cycle overhead
06/10/2003US6578105 Method of validating data in circular buffers
06/10/2003US6578094 Method for preventing buffer overflow attacks
06/10/2003US6578093 System for loading a saved write pointer into a read pointer of a storage at desired synchronization points within a horizontal video line for synchronizing data
06/10/2003CA2125289C Digital clock dejitter circuits for regenerating clock signals with minimal jitter
06/05/2003WO2003047113A1 Method of transferring data
06/05/2003WO2003046757A2 System and method for processing extensible markup language (xml) documents
06/05/2003US20030105985 Method and circuit for initializing a de-skewing buffer in a clock forwarded system
06/05/2003US20030105790 Galois field linear transformer
06/05/2003US20030102989 Coding apparatus and decoding apparatus
06/05/2003CA2467847A1 Method of transferring data
06/04/2003EP1317085A2 A method and circuit for initializing a de-skewing buffer in a clock forwarded system
06/04/2003EP1316955A1 Intermediate storage device
06/04/2003EP1316220A1 Method for compressing/decompressing structured documents
06/04/2003EP1316154A1 Hardware implementation of a compression algorithm
05/2003
05/30/2003WO2003044652A2 High-speed first-in-first-out buffer
05/29/2003US20030101324 Dynamic self-tuning memory management method and system
05/28/2003CN1110160C Data processing device including buffer memory
05/27/2003US6571378 Method and apparatus for a N-NARY logic circuit using capacitance isolation
05/27/2003US6571346 Elastic interface for master-slave communication
05/27/2003US6571320 Cache memory for two-dimensional data fields
05/27/2003US6571301 Multi processor system and FIFO circuit
05/27/2003US6571268 Multiplier accumulator circuits
05/27/2003US6571267 Floating point addition/subtraction execution unit
05/27/2003US6571264 Floating-point arithmetic device
05/27/2003US6571106 Method and apparatus for glitchless signal generation
05/27/2003US6570572 Line delay generator using one-port RAM
05/27/2003US6570403 Quantized queue length arbiter
05/22/2003WO2003042811A1 Efficient fifo communication using semaphores
05/22/2003WO2003042810A1 P- and v-semaphore operation
05/22/2003US20030097600 Communication clocking conversion techniques
05/22/2003US20030097526 High-speed first-in-first-out buffer
05/22/2003US20030097247 Data alignment between native and non-native shared data structures
05/22/2003US20030095054 Code converter and method of code conversion
05/21/2003EP1313006A2 Data transfer circuit between different clock regions
05/21/2003EP1080431B1 Data acquisition system comprising a circuit for converting a high frequency analog input signal into a plurality of digital signals
05/21/2003CN1419799A Communication port control module for lighting system
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