Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled
Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
08/2000
08/29/2000US6112268 System for indicating status of a buffer based on a write address of the buffer and generating an abort signal before buffer overflows
08/29/2000US6112267 Hierarchical ring buffers for buffering data between processor and I/O device permitting data writes by processor and data reads by I/O device simultaneously directed at different buffers at different levels
08/29/2000US6112250 Recompression of files at an intermediate node in a network system
08/29/2000US6111591 Image processing system and information processing system
08/24/2000WO2000049492A1 Transfer of very large digital data files via a fragmentation and reassembly methodology
08/24/2000WO2000049485A1 Method and circuit for receiving dual edge clocked data
08/24/2000CA2362174A1 Method and circuit for receiving dual edge clocked data
08/23/2000EP1029264A1 Remote control system which minimizes screen refresh time by selecting compression algorithm
08/22/2000US6108794 Signal comparison system and method for improving data analysis by determining transitions of a data signal with respect to a clock signal
08/16/2000EP1028369A2 System and method for automatic deskew across a high speed, parallel interconnection
08/16/2000EP1028365A2 Post write buffer for a dual clock system
08/16/2000EP1027649A1 Method of emulating a shift register using a ram
08/16/2000EP0680633B1 System for dynamically allocating memory registers for forming pseudo queues
08/15/2000US6105070 Method and apparatus for adjusting the buffering characteristic in the pipeline of a data transfer system
08/15/2000US6104642 Method and apparatus for 1 of 4 register file design
08/15/2000CA2205830C A processor for performing shift operations on packed data
08/10/2000WO2000046949A1 Synchronizing method and apparatus
08/10/2000WO2000046661A1 Self-adjusting elasticity buffer
08/09/2000CN1262479A Method and device for stabilizing image in display device
08/08/2000US6101516 Normalization shift prediction independent of operand subtraction
08/08/2000US6101329 System for comparing counter blocks and flag registers to determine whether FIFO buffer can send or receive data
08/03/2000WO2000038112A3 Code compaction by evolutionary algorithm
08/03/2000DE19904084A1 Computer with a large number of expansion cards with one or more having an on card processor and additional memory has four memory units on each card forming local expansion memory to speed data transfer between cards
08/03/2000DE10003376A1 Image stabilization device for display unit has motion compensation circuit functionally connected to motion sensor to compensate for movements of display unit so image remains static
08/02/2000EP1024600A2 Data compression method and data decompressing method, and data compressing apparatus and data decompressing apparatus therefor
08/01/2000US6098163 Three input arithmetic logic unit with shifter
08/01/2000US6098139 Frequency independent asynchronous clock crossing FIFO
08/01/2000US6098087 Method and apparatus for performing shift operations on packed data
08/01/2000US6097775 Method and apparatus for synchronously transferring signals between clock domains
08/01/2000US6097656 High speed empty flag generator
08/01/2000US6097655 Pull through FIFO memory device
08/01/2000CA2168284C Apparatus and associated method for compressing and decompressing digital data
07/2000
07/26/2000EP0897579B1 Memory device
07/25/2000US6094695 Storage buffer that dynamically adjusts boundary between two storage areas when one area is full and the other has an empty data register
07/25/2000US6094505 Information processing methodology
07/25/2000US6094436 Integrated multiport switch having shared media access control circuitry
07/19/2000CN1260546A Method and apparatus for storing and searching data in hand-held device
07/18/2000US6092171 System and method for using a memory management unit to reduce memory requirements
07/18/2000US6092129 Method and apparatus for communicating signals between circuits operating at different frequencies
07/18/2000US6092126 Asynchronous sample rate tracker with multiple tracking modes
07/18/2000US6091783 High speed digital data transmission by separately clocking and recombining interleaved data subgroups
07/18/2000US6091645 Programmable read ports and write ports for I/O buses in a field programmable memory array
07/18/2000US6091261 Apparatus and method for programmable delays using a boundary-scan chain
07/11/2000US6088776 Burst clock memory circuit
07/11/2000US6088745 Logical output queues linking buffers allocated using free lists of pointer groups of multiple contiguous address space
07/11/2000US6088744 Multiport data buffer having multi level caching wherein each data port has a FIFO buffer coupled thereto
07/11/2000US6088412 Elastic buffer to interface digital systems
07/11/2000US6087850 Operation circuit
07/04/2000US6084934 Natural throttling of data transfer across asynchronous boundaries
07/04/2000US6083274 Integrated structure layout and layout of interconnections for an integrated circuit chip
06/2000
06/29/2000WO2000038112A2 Code compaction by evolutionary algorithm
06/29/2000WO2000038063A2 Method and system for memory allocation in a multiprocessing environment
06/29/2000WO2000038045A1 Fifo unit with single pointer
06/29/2000CA2322138A1 Code compaction by evolutionary algorithm
06/28/2000EP1014648A2 Method and network device for creating buffer structures in shared memory
06/28/2000EP1012700A1 Multiple parallel identical finite state machines which share combinatorial logic
06/27/2000US6081904 Method for insuring data integrity during transfers
06/27/2000CA2095226C Apparatus for generating a ds-3 signal from the data component of an sts-1 payload signal
06/21/2000EP1011041A2 Data transfer apparatus, data transfer system and recording medium
06/21/2000EP1010053A1 Interface circuit for full-custom and semi-custom timing domains
06/20/2000US6078972 Control system of FIFO memories
06/20/2000US6078937 Barrel shifter, circuit and method of manipulating a bit pattern
06/20/2000US6078565 Method and apparatus to expand an on chip FIFO into local memory
06/13/2000US6075931 Method for efficient implementation of multi-ported logic FIFO structures in a processor
06/13/2000US6075833 Method and apparatus for counting signal transitions
06/13/2000US6075745 Field programmable memory array
06/13/2000US6075543 System and method for buffering multiple frames while controlling latency
06/08/2000WO2000033166A1 Automatic detection of 8b/10b data rates
06/07/2000EP1006435A1 A memory operated in a modified ping-pong mode
06/06/2000US6073245 Skewing-suppressive output buffer circuit
06/06/2000US6073228 Modulo address generator for generating an updated address
06/06/2000US6072741 First-in, first-out integrated circuit memory device incorporating a retransmit function
06/06/2000US6072185 Charged-particle-beam exposure device and method capable of high-speed data reading
06/06/2000CA2100753C Clock rate matching in independent networks
06/03/2000CA2287034A1 A memory operated in a modified ping-pong mode
05/2000
05/31/2000EP1004959A2 Processor with pipeline protection
05/30/2000US6070203 Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS
05/30/2000US6069554 Memory having both stack and queue operation
05/30/2000US6069497 Method and apparatus for a N-nary logic circuit using 1 of N signals
05/30/2000CA2233493C Asynchronous interface
05/30/2000CA2066229C Data compression apparatus
05/25/2000DE19850650A1 Verfahren zum Übertragen von Daten A method for transmitting data
05/17/2000EP1001378A2 Storage device and image data processing apparatus
05/16/2000US6065023 Spread sheet reading-out/collating apparatus, spread sheet reading-out/collating method, and a computer-readable recording medium with program making computer execute method stored therein
05/10/2000EP0999495A2 Procedure for the transfer of data
05/10/2000EP0970419A4 A lempel-ziv data compression technique utilizing a dicionary pre-filled with fequent letter combinations, words and/or phrases
05/10/2000CN1252573A Method and device for schedule display
05/09/2000US6061822 System and method for providing a fast and efficient comparison of cyclic redundancy check (CRC/checks sum) values of two mirrored disks
05/09/2000US6061802 Software based clock synchronization
05/09/2000US6061731 Read only linear stream based cache system
05/09/2000US6061398 Method of and apparatus for compressing and restoring data
05/09/2000US6061351 Multicopy queue structure with searchable cache area
05/04/2000DE19849909A1 Schaltungsanordnung zum Verarbeiten binärer Signale Circuitry for processing binary signals
05/03/2000EP0997813A2 Binary signal processing circuit
05/03/2000CN1052093C Fifo buffer system having enhanced controllability
05/02/2000US6058439 Asynchronous first-in-first-out buffer circuit burst mode control
05/02/2000US6058372 Interactive self-service hard drive copying system
05/02/2000US6058215 Reversible DCT for lossless-lossy compression
05/02/2000US6058156 Shift register device and method of driving the same
05/02/2000US6057789 Re-synchronization of independently-clocked audio streams by dynamically switching among 3 ratios for sampling-rate-conversion
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