G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled

Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
12/2002
12/12/2002	WO2002099621A1 Fifo buffer that can read and/or write a selectable number of data words per bus cycle
12/12/2002	WO2002099554A2 Power controlled electronic circuit
12/12/2002	US20020188885 DMA port sharing bandwidth balancing logic
12/12/2002	US20020188778 Consistency checking mechanism for configuration parameters in embedded systems
12/12/2002	US20020188773 Method and system for transferring and storing data in a medical device with limited storage and memory
12/12/2002	US20020188767 FIFO buffer that can read and/or write multiple and /or selectable number of data words per bus cycle
12/12/2002	DE10127423A1 Control of the energy used by cryptographic control circuits on chip cards, using device for determining energy available for controller so that processing performance is maximized
12/11/2002	EP1264234A2 Method and apparatus for ring buffer flow error detection
12/11/2002	EP0579595B1 Clock dejitter circuits for regenerating jittered clock signals
12/10/2002	US6493818 Technique for pipelining synchronization to maintain throughput across two asynchronous clock domain boundaries
12/10/2002	US6493794 Large scale FIFO circuit
12/10/2002	US6493277 Data generation circuit and method for data generating
12/05/2002	WO2002097620A2 Safe application distribution and execution in a wireless environment
12/05/2002	WO2002097607A1 Floating point system that represents status flag information within a floating point operand
12/05/2002	WO2002097606A1 Floating point multiplier with embedded status information
12/05/2002	WO2002097604A2 Floating point adder with embedded status information
12/05/2002	US20020184599 Data processing apparatus with circuit for confirming normality of serial transmission data
12/05/2002	US20020184414 System and method for checking bits in a buffer with multiple entries
12/05/2002	US20020184404 System and method of maintaining a timed event list
12/05/2002	US20020183056 Safe application distribution and execution in a wireless environment
12/05/2002	US20020180484 Semiconductor integrated circuit
12/04/2002	EP1263145A2 Method, apparatus, computer program and storage medium for data compression
12/03/2002	US6489969 Media composition system with media consolidation
12/03/2002	US6489805 Circuits, architectures, and methods for generating a periodic signal in a memory
11/2002
11/28/2002	WO2002063776A3 Method for compressing/decompressing a structured document
11/28/2002	US20020178392 Method and apparatus for generating a second signal having a clock based on a second clock from a first signal having a first clock
11/28/2002	US20020178311 Quantized queue length arbiter
11/28/2002	US20020178202 Floating point multiplier for delimited operands
11/28/2002	US20020178201 System and method for extracting the high part of a floating point operand
11/28/2002	US20020178200 Circuit for selectively providing maximum or minimum of a pair of floating point operands
11/28/2002	US20020178199 Floating point status information testing circuit
11/28/2002	US20020178198 Comparator unit for comparing values of floating point operands
11/28/2002	US20020178197 System and method for generating an integer part of a logarithm of a floating point operand
11/28/2002	US20020175840 Method, apparatus, computer program and storage medium for data compression
11/27/2002	CN1095130C Adjustable depth/width FIFO buffer for width changeable data transfer
11/26/2002	US6487576 Zero anticipation method and apparatus
11/26/2002	US6487212 Queuing structure and method for prioritization of frames in a network switch
11/26/2002	US6486704 Programmable burst FIFO
11/21/2002	WO2002093392A1 Data processor
11/21/2002	WO2002093358A1 System and method for encoding and decoding data files
11/21/2002	US20020174273 Self-adjusting elasticity buffer
11/21/2002	US20020172319 Method and apparatus for gathering queue performance data
11/21/2002	US20020172311 Large-input-delay variation tolerant (lidvt) receiver adopting FIFO mechanism
11/21/2002	US20020172310 Jitter attenuator fifo overflow-underflow protection using digital-phase locked loop's bandwidth adaptation
11/21/2002	US20020171452 Circuits, architectures, and methods for generating a periodic signal in a memory
11/21/2002	DE10122702A1 Producing second signal with clock based on second clock from first signal with first clock involves sampling first signal using second clock, phase shifted clock to detect defined logical state
11/20/2002	EP1258798A2 Data transfer control device, electronic equipment, and data transfer control method
11/14/2002	WO2002091188A1 Method and apparatus for gathering queue performance data
11/14/2002	US20020169905 Data transfer control device, electronic equipment, and data transfer control method
11/14/2002	US20020169789 System and method for accessing, organizing, and presenting data
11/14/2002	US20020167434 Fast A/D conversion signal processor, RF receiver circuit, digital receiver front end circuit, MRI apparatus, and fast A/D conversion device
11/14/2002	US20020167424 Data processing apparatus, data processing method, program, program recording medium, embedded data, and data recording medium
11/14/2002	US20020167337 Low latency FIFO circuits for mixed asynchronous and synchronous systems
11/14/2002	DE10121745A1 Verfahren und Anordnung zu einem Stack mit einem, in Datengruppen mit mehreren Elementen aufgeteilten Speicher Method and arrangement in a stack with one, in groups of data with multiple elements divided memory
11/14/2002	DE10121461A1 Method of compensating for clock shift between bluetooth communications subscriber and transmitting module, has transmitting module communicating with subscriber/host
11/13/2002	EP1256874A2 Fast A/D conversion signal processor, and fast A/D conversion device
11/13/2002	EP1256237A1 Improvements in or relating to data compression
11/12/2002	US6480942 Synchronized FIFO memory circuit
11/12/2002	US6480912 Method and apparatus for determining the number of empty memory locations in a FIFO memory device
11/12/2002	US6480910 Digital interface unit with selective input registers providing control values to output registers that simultaneously output the control values when activated by control line
11/07/2002	WO2002088928A2 Method and device for adapting the data rate of a data stream
11/07/2002	US20020166021 Method and arrangement in a stack having a memory segmented into data groups having a plurality of elements
11/07/2002	US20020166008 Data processing system and multiprocessor system
11/07/2002	US20020165733 Method and system for detecting variances in a tracking environment
11/07/2002	US20020163363 Source synchronous I/O using temporal delay queues
11/07/2002	US20020163361 Source synchronous I/O without synchronizers using temporal delay queues
11/07/2002	DE10121198A1 Verfahren und Vorrichtung zur Anpassung der Datenrate eines Datenstroms Method and apparatus for adapting the data rate of a data stream
11/07/2002	DE10121196A1 FIFO memory is used to allow different data rates by controlling input and output rates
11/05/2002	US6477637 Method and apparatus for transporting store requests between functional units within a processor
11/05/2002	US6477165 Broadcast command packet protocol for SCSI interface
10/2002
10/31/2002	US20020161949 Data transmission by an alternating frequency analog signal
10/30/2002	EP1252564A1 Method and apparatus for increasing the battery life of portable electronic devices
10/30/2002	EP0847552B1 An apparatus for performing multiply-add operations on packed data
10/24/2002	WO2002003206A3 Multientity queue pointer chain tehnique
10/24/2002	US20020156990 Modulus address generator and method for determining a modulus address
10/24/2002	US20020156818 Microprocessor comprising an instruction for inverting bits in a binary word
10/24/2002	US20020154640 Method of clock mismatch and drift compensation for packet networks
10/23/2002	EP1099153B1 Storage device and a method for operating the storage device
10/22/2002	US6470439 FIFO memory control circuit
10/22/2002	US6470415 Queue system involving SRAM head, SRAM tail and DRAM body
10/22/2002	US6470402 Increasing values of a read and a trigger pointers when a write pointer reaches the read pointer in a circular FIFO (first-in-first-out) store
10/17/2002	WO2002082348A2 Method and system for detecting variances in a tracking environment
10/17/2002	US20020150189 Apparatus and method for generating a distributed clock signal using gear ratio techniques
10/17/2002	US20020149978 Format-converting device and private branch exchange system using the same, and format-converting method and memory medium storing a program to allow computer to execute the same method
10/17/2002	DE10210663A1 Device for indication of and/or precise operations on numerical values in binary system divides binary coded number by divisor, use results to look up display screen codes in static table
10/16/2002	EP0960510B1 Split-queue architecture and method of queuing
10/15/2002	US6466998 Interrupt routing mechanism for routing interrupts from peripheral bus to interrupt controller
10/15/2002	US6466699 Reversible DCT for lossless—lossy compression
10/15/2002	US6466219 Storage device and image data processing apparatus
10/10/2002	WO2002079971A1 Programmable cpu/interface buffer structure using dual port ram
10/10/2002	WO2002050655A3 Fifo buffer with output rate adjusting
10/10/2002	WO2002027464A3 Asynchronous implementation of a multi-dimensional, low latency, first-in, first-out (fifo) buffer
10/10/2002	WO2001037076A3 Method and apparatus for ring buffer flow error detection
10/08/2002	US6463485 System for providing cell bus management in a switch platform including a write port cell count in each of a plurality of unidirectional FIFO for indicating which FIFO be able to accept more cell
10/08/2002	US6463000 First-in first-out memory device and method of generating flag signal in the same
10/03/2002	WO2002078227A2 Communication of latencies in parallel networks
10/03/2002	WO2002077829A2 A communication system
10/03/2002	US20020144170 Computer system having memory device with adjustable data clocking using pass gates
10/03/2002	US20020144169 DS-3 desynchronizer
10/03/2002	US20020144031 Method and apparatus for budget development under universal serial bus protocol in a multiple speed transmission environment

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