Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled
Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
05/2003
05/21/2003CN1109349C 缓冲存储器控制器 Cache controller
05/20/2003US6567094 System for controlling read and write streams in a circular FIFO buffer
05/15/2003WO2002078227A3 Communication of latencies in parallel networks
05/15/2003US20030093656 Processor with a computer repeat instruction
05/15/2003US20030093637 Command order maintenance scheme for multi-in/multi-out FIFO in multi-threaded I/O links
05/15/2003US20030093629 Buffer management method and a controller thereof
05/15/2003US20030091241 Data compressing apparatus, reconstructing apparatus, and its method
05/14/2003EP1309908A1 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system
05/14/2003CN1417970A 电路结构 Circuit structure
05/14/2003CN1108562C Compression data expanded circuit and expanding method thereof
05/13/2003US6563956 Method and apparatus for compressing data string
05/13/2003US6563438 Encoding and decoding apparatus with matching length means for symbol strings
05/08/2003WO2003039061A2 Clock domain crossing fifo
05/08/2003US20030086620 System and method for split-stream dictionary program compression and just-in-time translation
05/08/2003US20030086372 Automatic adjustment of buffer depth for the correction of packet delay variation
05/08/2003DE4244920C2 Clock rate matching for independent networks
05/07/2003EP1308913A1 Intelligent electrical devices
05/07/2003EP1166210B1 Elastic interface apparatus and method therefor
05/07/2003EP1116098B1 Method and device for writing and reading a buffer memory
05/07/2003CN1108014C Variable-length code encoding and segmenting appts. having byte alignment unit
05/07/2003CN1107905C Appts. for performing multiply-add operations on packed data
05/06/2003US6560691 Modulus address generator and method for determining a modulus address
05/02/2003EP1306747A1 Circuitry for signal transmission between state machines operating at different clock frequencies
05/01/2003WO2003036475A1 Data alignment between native and non-native shared data structures
05/01/2003WO2002031664A3 System, method and article of manufacture for data transfer across clock domains
05/01/2003US20030081713 Clock domain crossing fifo
05/01/2003US20030081708 Circuit configuration
04/2003
04/30/2003CN1414480A Method of access arbitrary bit range data between different platforms
04/29/2003US6557109 Synchronizing device and method that adjusts readout speed according to remaining quantity of data in memory while operating decoder on fixed frequency system clock
04/29/2003US6557097 Linear vector computation
04/29/2003US6557096 Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
04/29/2003US6557053 Queue manager for a buffer
04/29/2003US6556495 2-D FIFO memory having full-width read/write capability
04/29/2003US6556156 Circuit and method for calibrating the phase shift between a plurality of digitizers in a data acquisition system
04/24/2003WO2001082053A3 A low latency fifo circuit for mixed clock systems
04/24/2003US20030079059 Interface between different clock rate components
04/24/2003US20030078950 Method and system for performing shift operations
04/24/2003DE10158810C1 Fixed point signal division circuit converts input signal into fixed point output signal by division by variable power of 2
04/23/2003EP1304850A2 Ethernet device and method for extending ethernet fifo buffer
04/23/2003EP0974099B1 Video graphics controller having locked and unlocked modes of operation
04/22/2003US6553503 Circuitry, architecture and method(s) for synchronizing data
04/22/2003US6553448 Method for unit distance encoding of asynchronous pointers for non-power-of-two sized buffers
04/22/2003US6553424 Circular buffer for a TDMA data transmission station and corresponding data transmission station
04/22/2003US6553142 Quantization table adjustment
04/22/2003US6552590 Clocking scheme for ASIC
04/17/2003WO2003032157A1 Compiler
04/17/2003WO2003032147A2 Method and apparatus for buffer storage of data packets which are to be transmitted via a connection that has been set up
04/17/2003US20030074609 System and method for automatic deskew across a high speed, parallel interconnection
04/17/2003US20030074593 Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain
04/17/2003US20030074543 A processor with apparatus for verifying instruction parallelism
04/16/2003EP1302858A1 Data processing system, and data processing method
04/16/2003EP1302848A2 A microprocessor having a multiply operation
04/16/2003CN1410877A High speed floating point addition and subtraction part capable of direct matching exponents and need not calculating exponential difference
04/16/2003CN1106081C Code translation circuit
04/15/2003US6549593 Interface apparatus for interfacing data to a plurality of different clock domains
04/15/2003US6549148 Encoding and decoding apparatus using context
04/10/2003WO2003029953A2 Method for storing or transferring data
04/10/2003WO2002071249A9 Method and devices for treating and/or processing data
04/10/2003US20030070020 Bus control system
04/10/2003US20030069912 Apparatus and method for precision binary numbers and numerical operations
04/08/2003US6546516 Method and apparatus for measuring timing characteristics of message-oriented transports
04/08/2003US6546461 Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein
04/08/2003US6546143 Efficient wavelet-based compression of large images
04/03/2003US20030065892 Concurrent non-blocking FIFO array
04/03/2003US20030063567 Ethernet device and method for extending ethernet FIFO buffer
04/01/2003US6542999 System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock
04/01/2003US6542640 Data compressing apparatus, reconstructing apparatus, and its method
03/2003
03/27/2003US20030061418 Efficient reading of a remote first in first out buffer
03/27/2003US20030061413 Buffer partitioning for managing multiple data streams
03/26/2003EP1296221A1 Control structure for a high-speed asynchronous pipeline
03/26/2003EP1296220A2 Buffer partitioning for managing multiple data streams
03/26/2003EP1204917B1 Stack of operands and method for stacking of operands
03/26/2003EP1183584B1 Fft processor with overflow prevention
03/26/2003CN1104094C Data compression method and apparatus
03/25/2003US6539488 System with a plurality of media access control circuits with a shared memory for storing data and synchronizing data from a clock domain to a host clock domain
03/25/2003US6539465 Method and apparatus for byte alignment operations for a memory device that stores an odd number of bytes
03/25/2003US6538999 PID filter circuit and FIFO circuit
03/25/2003US6538470 Devices and methods with programmable logic and digital signal processing regions
03/25/2003US6538467 Multi-access FIFO queue
03/20/2003WO2003023600A2 An apparatus and method for extracting and loading data to/from a buffer
03/20/2003US20030056137 Method and apparatus for writing data between fast and slow clock domains
03/20/2003US20030056073 Queue management method and system for a shared memory switch
03/20/2003US20030056039 Data buffer
03/20/2003US20030055860 Rounding mechanisms in processors
03/20/2003US20030053367 2-D FIFO memory having full-width read/write capability
03/20/2003US20030052708 Methods and circuitry for implementing first-in first-out structure
03/19/2003EP1293888A2 Methods and circuitry for implementing first-in first-out structure
03/18/2003US6535946 Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock
03/18/2003US6533172 Property security system and method therefor
03/12/2003CN1402122A Edition identifying device with A/D conversion function, and method
03/06/2003WO2003019351A2 Fifo memory devices having single data rate (sdr) and dual data rate (ddr) capability
03/06/2003WO2003019350A1 Buffer system with sequential and non-sequential block access
03/06/2003US20030046498 Synchronization of non-sequential moving pointers
03/06/2003US20030043639 System and method for managing configurable buffer sizes
03/06/2003US20030043156 Apparatus and method for extracting and loading data to/from a buffer
03/05/2003EP1289153A2 Data compressing method and data decompressing method, and data compressing apparatus and data decompressing apparatus therefor
03/05/2003EP1288777A2 Buffer storage system
03/05/2003CN1102812C Method and apparatus for executing a sequential data compression algorithm
03/04/2003US6529971 Adaptive elasticity FIFO buffer
03/04/2003US6529912 Data compressing apparatus and a data decompressing apparatus, a data compressing method and a data decompressing method, and a data compressing or decompressing dictionary creating apparatus and a computer readable recording medium storing a data compressing program or a data decompressing program
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