| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 02/28/2003 | CA2399920A1 System and method for managing configurable buffer sizes |
| 02/27/2003 | WO2003017541A1 Variable size first in first out (fifo) memory with head and tail caching |
| 02/27/2003 | WO2002097604A3 Floating point adder with embedded status information |
| 02/27/2003 | US20030039354 FIFO architecture with in-place cryptographic service |
| 02/26/2003 | EP1286257A2 Conditional subtract instruction |
| 02/25/2003 | US6526495 Multiport FIFO with programmable width and depth |
| 02/25/2003 | US6526451 Method and network device for creating circular queue structures in shared memory |
| 02/25/2003 | US6526068 Interface control of communication between a control processor and a digital signal processor |
| 02/25/2003 | US6525980 High speed FIFO synchronous programmable full and empty flag generation |
| 02/25/2003 | US6525679 Binary to decimal coder/decoder |
| 02/25/2003 | CA2128127C Method and system for data compression |
| 02/20/2003 | US20030037210 System for head and tail caching |
| 02/20/2003 | US20030037096 Method and apparatus for the management of queue pointers by multiple processors in a digital communications network |
| 02/20/2003 | US20030037088 Speed of execution of a conditional subtract instruction and increasing the range of operands over which the instruction would be performed correctly |
| 02/20/2003 | US20030035012 System for accessing a large number of menu items using a zoned menu bar |
| 02/20/2003 | US20030034905 System and method for encoding and decoding data files |
| 02/20/2003 | US20030034824 Shifting an operand left or right while minimizing the number of multiplexor stages |
| 02/20/2003 | US20030034797 Multi-access fifo queue |
| 02/19/2003 | CN1398488A Improvements in relating to data compression |
| 02/18/2003 | US6523060 Method and apparatus for the management of queue pointers by multiple processors in a digital communications network |
| 02/13/2003 | WO2003012648A1 Data formatter employing data shifter based on the destination address |
| 02/13/2003 | US20030033552 Apparatus and method for wait state analysis in a digital signal processing system |
| 02/13/2003 | US20030033508 Endian transformation |
| 02/13/2003 | US20030033499 Method and system for circular addressing with efficient memory usage |
| 02/13/2003 | US20030033134 Endian transformation |
| 02/13/2003 | US20030030643 Method and apparatus for updating state data |
| 02/13/2003 | CA2454467A1 Data formatter employing data shifter based on the destination address |
| 02/11/2003 | US6519722 Method and apparatus for controlling the read clock signal rate of a first-in first-out (FIFO) data memory |
| 02/11/2003 | US6519667 Bus control system |
| 02/11/2003 | US6519188 Circuit and method for controlling buffers in semiconductor memory device |
| 02/06/2003 | US20030028748 Circuit for recording digital waveform data and method of doing the same |
| 02/06/2003 | US20030028702 Data reordering mechanism for data transfer in computer systems |
| 02/05/2003 | EP1183596A4 Generating optimized computer data field conversion routines |
| 02/04/2003 | US6516420 Data synchronizer using a parallel handshaking pipeline wherein validity indicators generate and send acknowledgement signals to a different clock domain |
| 02/04/2003 | US6516408 Various length software breakpoint in a delay slot |
| 02/04/2003 | US6516362 Synchronizing data between differing clock domains |
| 02/04/2003 | US6516359 Information processing method and apparatus, automotive information system and method of controlling the same, and storage medium on which an information processing program is stored |
| 01/30/2003 | US20030023819 Data formatter |
| 01/30/2003 | US20030023789 Implementing method for buffering devices |
| 01/30/2003 | US20030023787 Glitch suppression circuit and method |
| 01/30/2003 | US20030023396 Random number indexing method and apparatus that eliminates software call sequence dependency |
| 01/30/2003 | US20030020639 Encoding and decoding apparatus using context |
| 01/28/2003 | US6513126 System for modeling a processor-encoder interface by counting number of fast clock cycles occuring in one slower clock cycle and triggering a domain module if fast clock reaches the corresponding number of cycles |
| 01/28/2003 | US6513105 FIFO system with variable-width interface to host processor |
| 01/28/2003 | US6513055 Apparatus and method for data width reduction in automotive systems |
| 01/23/2003 | WO2003007614A2 Method for compressing a hierarchical tree, corresponding signal and method for decoding a signal. |
| 01/23/2003 | WO2003007517A1 Automatic adjustment of buffer depth |
| 01/23/2003 | US20030018867 Method to manage multiple communication queues in an 8-bit microcontroller |
| 01/23/2003 | US20030018862 Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same |
| 01/23/2003 | US20030018839 Data transfer control device and electronic equipment |
| 01/23/2003 | US20030018676 Multi-function floating point arithmetic pipeline |
| 01/23/2003 | US20030018466 XML data encoding and decoding |
| 01/22/2003 | EP1277112A2 Capturing of a register value to another clock domain |
| 01/21/2003 | US6510486 Clocking scheme for independently reading and writing multiple width words from a memory array |
| 01/21/2003 | US6510446 Floating point calculation method and unit efficiently representing floating point data as integer and semiconductor integrated circuit device provided with the same |
| 01/16/2003 | US20030014455 Floating point multiplier with embedded status information |
| 01/15/2003 | EP1276324A1 Method for compressing a hierarchical tree, corresponding signal and method for decoding a signal |
| 01/14/2003 | US6507921 Trace fifo management |
| 01/09/2003 | US20030009653 Apparatus and method for converting binary numbers to character codes |
| 01/09/2003 | US20030009644 Bi-directional RAM for data transfer using two clock frequencies having no multiple relation |
| 01/09/2003 | US20030009596 Method for programming code compression using block sorted compression algorithm, processor system and method for an information delivering service using the code compression |
| 01/09/2003 | US20030007396 Direct memory access controller for circular buffers |
| 01/08/2003 | CN1389795A Dada processing apparatus with circuit for determining serial transmission data proper characteristic |
| 01/08/2003 | CN1389784A Method of raising the resolution degree of moving cursor on display screen |
| 01/07/2003 | US6505239 System for minimizing screen refresh time using selectable compression speeds |
| 01/07/2003 | US6504415 Clock distribution for improved jitter performance in high-speed communication circuits |
| 01/03/2003 | WO2003001360A2 First-in, first-out memory system and method thereof |
| 01/02/2003 | US20030005348 Clock reproducing method and receiving clock producing apparatus |
| 01/02/2003 | US20030005344 Synchronizing data with a capture pulse and synchronizer |
| 01/02/2003 | US20030005259 System and method for device support |
| 01/02/2003 | US20030005141 Information-processing apparatus, information-processing method, network system, and program |
| 01/02/2003 | US20030005015 Vector scaling system for G.728 annex G |
| 01/02/2003 | US20030005013 Floating point system that represents status flag information within a floating point operand |
| 01/02/2003 | US20030002741 Quantization table adjustment |
| 01/02/2003 | US20030001759 Encoding and decoding apparatus with matching length means for symbol strings |
| 01/02/2003 | EP1271836A1 Bi-directional serial data transmission |
| 01/02/2003 | EP1271315A2 Run queue management |
| 01/02/2003 | EP1271312A2 System and method for split-stream dictionary program compression and just-in-time translation |
| 01/02/2003 | EP1271284A2 Timing signal generating system |
| 01/01/2003 | CN1388443A Method and apparatus for data compression, computer program and storage media |
| 12/31/2002 | US6501395 System, method and computer readable medium for compressing a data sequence |
| 12/26/2002 | US20020199124 System and method for synchronizing data transfer across a clock domain boundary |
| 12/26/2002 | US20020199042 First-in, first-out memory system and method thereof |
| 12/26/2002 | US20020198917 Floating point adder with embedded status information |
| 12/26/2002 | US20020198916 Method and circuit for normalization of floating point significands in a SIMD array MPP |
| 12/26/2002 | US20020196889 Timing signal generating system and receiving circuit for transmitting signals at high speed with less circuitry |
| 12/26/2002 | US20020196166 Data compression method and data compression apparatus |
| 12/24/2002 | US6499111 Apparatus for adjusting delay of a clock signal relative to a data signal |
| 12/24/2002 | US6499098 Processor with instruction qualifiers to control MMU operation |
| 12/24/2002 | US6499080 Post write buffer for a dual clock system |
| 12/19/2002 | WO2002101938A2 Method and circuit for transmitting data from a system which is operated by means of a first clock pulse to a system which is operated by means of a second clock pulse |
| 12/19/2002 | US20020194520 Apparatus and method for clock domain crossing with integrated decode |
| 12/19/2002 | US20020194519 Programmable interface controller suitable for spanning clock domains |
| 12/19/2002 | US20020194452 Modulo addressing based on absolute offset |
| 12/19/2002 | US20020194249 Run queue management |
| 12/19/2002 | US20020194238 Method and circuit for alignment of floating point significands in a SIMD array MPP |
| 12/19/2002 | US20020190877 Encoding and decoding apparatus with matching length means for symbol strings |
| 12/19/2002 | US20020190753 Programmable burst fifo |
| 12/18/2002 | CN1385793A Data transmission controller, electronic machine and data transmission control method |
| 12/18/2002 | CN1385135A Quick analog-to-digital convertion signal processor, RF receiving circuit, digital receiving front circuit |