| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 06/27/2002 | US20020083100 Converting method for converting documents between different locales |
| 06/27/2002 | US20020080672 First-in first-out memory device and method of generating flag signal in the same |
| 06/26/2002 | EP1217536A2 Converting method for converting documents between different locales |
| 06/26/2002 | CN1355920A Data transfer apparatus, data transfer system, and data transfer method with double buffering |
| 06/25/2002 | US6411980 Data split parallel shifter and parallel adder/subtractor |
| 06/25/2002 | US6411978 Mechanism for block floating point FFT hardware support on a fixed point digital signal processor |
| 06/21/2002 | CA2342068A1 Converting method for converting documents between different locales |
| 06/20/2002 | WO2000057268A9 Generating optimized computer data field conversion routines |
| 06/20/2002 | US20020078468 Data processor for outputting data according to their types |
| 06/20/2002 | US20020078317 First-in, first-out (FIFO) memory with moving boundary |
| 06/20/2002 | US20020078109 Shift and detecting circuit and floating-point calculating circuit using the same |
| 06/20/2002 | US20020075887 FIFO storage including pointer misalignment detection |
| 06/20/2002 | US20020075173 Parallel in serial out circuit for use in data communication system |
| 06/19/2002 | CN1354425A Serial/parallel change-over circuit, data transmitting control device and electronic equipment |
| 06/19/2002 | CN1086521C Integrated circuit, system and method for reducing distortion between clock signal and data signal |
| 06/18/2002 | US6408409 Method and apparatus for ring buffer flow error detection |
| 06/18/2002 | US6408349 Adjustable elasticity fifo buffer have a number of storage cells equal to a frequency offset times a number of data units in a data stream |
| 06/18/2002 | US6408077 Descrambling device of a security element and security element comprising such a device |
| 06/12/2002 | EP1080433B1 CIRCUIT AND METHOD FOR CALIBRATING PHASE SHIFT BETWEEN A PLURALITY OF Analog-digital-converter in a DATA ACQUISITION SYSTEM |
| 06/12/2002 | EP0787327B1 Data processing system comprising an asynchronously controlled pipeline |
| 06/11/2002 | US6405269 FIFO memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers |
| 06/11/2002 | US6405233 Unaligned semaphore adder |
| 06/11/2002 | US6405232 Leading bit prediction with in-parallel correction |
| 06/06/2002 | WO2002003629A3 Connection shaping control technique implemented over a data network |
| 06/06/2002 | WO2002003612A3 Technique for assigning schedule resources to multiple ports in correct proportions |
| 06/06/2002 | US20020069375 System, method, and article of manufacture for data transfer across clock domains |
| 06/05/2002 | EP0962077B1 Integrated multiport switch having management information base (mib) interface temporary storage |
| 06/04/2002 | US6401232 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
| 06/04/2002 | US6401213 Timing circuit for high speed memory |
| 06/04/2002 | US6401148 FIFO memory system and method with improved determination of amount of data stored using a binary read address synchronized to a write clock |
| 06/04/2002 | US6400614 Transmission device and integrated circuit |
| 06/04/2002 | US6400291 Multiple time domain serial-to-parallel converter |
| 06/04/2002 | US6400197 Delay device having a delay lock loop and method of calibration thereof |
| 05/30/2002 | WO2001053942A3 Double-ended queue with concurrent non-blocking insert and remove operations |
| 05/28/2002 | US6397318 Address generator for a circular buffer |
| 05/28/2002 | US6397289 Disk control apparatus |
| 05/28/2002 | US6397276 Data transmission by an alternating-frequency analog signal |
| 05/28/2002 | US6396887 Apparatus and method for generating a distributed clock signal using gear ratio techniques |
| 05/23/2002 | WO2001082081A3 Capturing of a register value to another clock domain |
| 05/22/2002 | EP1207640A2 Method and apparatus for reducing clock speed and power consumption |
| 05/21/2002 | US6393575 Semiconductor device having input buffers |
| 05/21/2002 | US6393487 Passing a communication control block to a local device such that a message is processed on the device |
| 05/21/2002 | US6393446 32-bit and 64-bit dual mode rotator |
| 05/16/2002 | US20020059488 Data transfer control device and electronic instrument |
| 05/16/2002 | US20020059426 Technique for assigning schedule resources to multiple ports in correct proportions |
| 05/16/2002 | US20020059307 Method for transforming data formats between different database systems, an apparatus for executing the method and the program of the method |
| 05/15/2002 | EP1206168A1 Intelligent electrical devices |
| 05/15/2002 | EP1204917A1 Stack of operands and method for stacking of operands |
| 05/15/2002 | EP1163569A4 Method and circuit for receiving dual edge clocked data |
| 05/14/2002 | US6389490 FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals |
| 05/14/2002 | US6389489 Data processing system having a fifo buffer with variable threshold value based on input and output data rates and data block size |
| 05/09/2002 | US20020056021 Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same |
| 05/08/2002 | EP0804762B1 Self-diagnostic asynchronous data buffers |
| 05/08/2002 | CN1348291A Serial communication equipment and method for executing serial communication |
| 05/07/2002 | US6385717 Programmable 1-bit data processing arrangement |
| 05/07/2002 | US6385672 System to optimize packet buffer utilization via selectively partitioned transmit and receive buffer portions |
| 05/07/2002 | US6385656 Selective recompression of files in a network system |
| 05/07/2002 | US6384634 Elastic store: recovery and boundary verification |
| 05/02/2002 | US20020052989 Data processing apparatus and data processing method |
| 05/02/2002 | US20020052664 Signal processing apparatus |
| 05/02/2002 | EP1202163A2 Serial/parallel conversion circuit, data transfer control device, and electronic equipment |
| 04/30/2002 | US6381659 Method and circuit for controlling a first-in-first-out (FIFO) buffer using a bank of FIFO address registers capturing and saving beginning and ending write-pointer addresses |
| 04/25/2002 | WO2002033537A1 Multiplier and shift device using signed digit representation |
| 04/25/2002 | US20020049872 Serial/parallel conversion circuit, data transfer control device, and electronic equipment |
| 04/25/2002 | US20020049581 Physical medium dependent sub-system with shared resources for multiport xDSL system |
| 04/25/2002 | US20020047595 Intelligent electrical switching devices. |
| 04/24/2002 | CN1346129A Method for regulating threshold value of first-in first-out buffer |
| 04/23/2002 | US6378079 Computer system having memory device with adjustable data clocking |
| 04/23/2002 | US6378057 Data processing apparatus |
| 04/23/2002 | US6377929 Solid-state audio recording unit |
| 04/23/2002 | US6377077 Clock supply circuit and data transfer circuit |
| 04/23/2002 | US6377071 Composite flag generation for DDR FIFOs |
| 04/18/2002 | WO2002031664A2 System, method and article of manufacture for data transfer across clock domains |
| 04/18/2002 | WO2001053943A3 Double-ended queue with concurrent non-blocking insert and remove operations |
| 04/18/2002 | US20020046366 Serial communication device and method of carrying out serial communication |
| 04/18/2002 | US20020046307 A data buffer |
| 04/17/2002 | EP1120018B1 Intelligent electrical devices |
| 04/17/2002 | CN1345027A Performing information recording device, compression device, decoding device and telephone terminal device |
| 04/16/2002 | US6374361 Skew-insensitive low voltage differential receiver |
| 04/16/2002 | US6374360 Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
| 04/16/2002 | US6374313 FIFO and method of operating same which inhibits output transitions when the last cell is read or when the FIFO is erased |
| 04/16/2002 | US6373986 Compression of data transmission by use of prime exponents |
| 04/16/2002 | US6373408 Encoding apparatus, decoding apparatus, encoding/decoding apparatus, encoding method and decoding method |
| 04/11/2002 | US20020042890 Digital microelectronic circuit with a clocked data-processing unit and a converting unit |
| 04/11/2002 | US20020042708 Method and apparatus for outputting a datastream processed by a processing device |
| 04/11/2002 | US20020041599 Method and apparatus for reducing clock speed and power consumption |
| 04/11/2002 | DE10145961A1 System und Verfahren zum Kalibrieren einer Steuereinheit System and method of calibrating a control unit |
| 04/10/2002 | EP0806004B1 Data transmission system with a data buffer having a tree shaped structure of multiplexers |
| 04/10/2002 | CN1343897A Mirror shift control system for large astronomical telescope |
| 04/09/2002 | US6370600 Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency |
| 04/04/2002 | WO2002027464A2 Asynchronous implementation of a multi-dimensional, low latency, first-in, first-out (fifo) buffer |
| 04/04/2002 | US20020040369 Binary data synchronization engine |
| 04/03/2002 | EP1193606A2 Apparatus and method for a host port interface unit in a digital signal processing unit |
| 04/03/2002 | CN1343335A Elastic interface apparatus and method therefor |
| 04/03/2002 | CN1343050A Input data processing circuit |
| 04/02/2002 | US6367027 Skew pointer generation |
| 04/02/2002 | US6366530 Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding |
| 04/02/2002 | US6366529 Fast FiFo memory storage system |
| 03/28/2002 | WO2000046661A9 Self-adjusting elasticity buffer |
| 03/28/2002 | US20020038410 Write buffer for use in a data processing apparatus |