Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled
Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
11/2003
11/19/2003CN1128410C Team manager and method for controlling inputting data into system from external source
11/18/2003US6651146 Method and apparatus for managing access contention to a linear list without the use of locks
11/18/2003US6650256 Data processing apparatus, data processing method, program, program recording medium, embedded data, and data recording medium
11/18/2003US6650066 Intelligent electrical switching device
11/13/2003US20030212831 Image processing device and image processing method
11/11/2003US6647499 System for powering down a disk storage device to an idle state upon trnsfer to an intermediate storage location accessible by system processor
11/11/2003US6647445 Data transmission by an alternating frequency analog signal
11/11/2003US6647444 Data synchronization interface
11/06/2003US20030206475 FIFO memory devices that support all combinations of DDR and SDR read and write modes
11/05/2003EP1358542A1 Method and system for buffering streamed data
11/05/2003CN1454347A Multiplier and shift device using signed digit representation
11/05/2003CN1127244C Method of controlling time mark bias and equipment for transmitting packet by using said method
11/05/2003CN1127219C Method for compressing and decompressing data files
11/04/2003US6643793 Apparatus for transferring and holding data based on a selected clock rate
11/04/2003US6643789 Computer system having memory device with adjustable data clocking using pass gates
11/04/2003US6643719 Equalizing FIFO buffer with adaptive watermark
11/04/2003US6643673 Method and apparatus for arithmetic shifting
11/04/2003US6643414 Image processing method, image processing apparatus, and data storage media
11/04/2003US6643263 Device and method for buffer protection
11/04/2003US6642860 Data compression method and system that use a regressive string reference, pointing to and delimiting an encoded pointee string, and identify the reference through a signalling element, an encoding device and a decoding device arranged for implementing the method, and a storage medium provided with information produced by such encoding device and/or arranged for decoding by such decoding device
10/2003
10/30/2003WO2003090064A1 Circuit, apparatus and method for storing audiovisual data
10/30/2003WO2003090063A2 Output rate change
10/30/2003WO2002071249A8 Method and devices for treating and/or processing data
10/30/2003WO2002071196A8 Methods and devices for treating and processing data
10/29/2003EP1356712A1 Communication port control module for lighting systems
10/29/2003EP1356595A2 Method for compressing/decompressing a structured document
10/29/2003EP1356383A2 Intermediate buffer control for improving throughput of split transaction interconnect
10/29/2003EP0960502B1 Method and apparatus for transmitting multiple copies by replicating data identifiers
10/29/2003CN1126106C Storage integrated circuit and main storage system using same and figure storage system thereof
10/28/2003US6640277 Input staging logic for latching source synchronous data
10/28/2003US6640267 Architecture for multi-queue storage element
10/23/2003WO2003039061A3 Clock domain crossing fifo
10/23/2003WO2002082348A3 Method and system for detecting variances in a tracking environment
10/23/2003US20030200366 Data transmission apparatus and electronic control unit
10/23/2003US20030199262 Multi-clock domain data input-processing device having clock-reciving locked loop and clock signal input method thereof
10/23/2003US20030198287 Frequency converter
10/22/2003EP1354411A1 Data compression method with identifier of regressive string reference
10/22/2003EP0861490B1 Recording and reproducing system for simultaneous recording and reproduction via an information carrier
10/21/2003US6636993 System and method for automatic deskew across a high speed, parallel interconnection
10/16/2003WO2003007614A3 Method for compressing a hierarchical tree, corresponding signal and method for decoding a signal.
10/16/2003WO2003001360A3 First-in, first-out memory system and method thereof
10/16/2003WO2001095089A3 Low latency fifo circuits for mixed asynchronous and synchronous systems
10/16/2003US20030196010 Non-blocking concurrent queues with direct node access by threads
10/16/2003US20030196009 Audio buffer station allocation
10/16/2003US20030195914 Sparse-coefficient functions for reducing computational requirements
10/16/2003US20030194137 Quantization table adjustment
10/15/2003CN1124609C Semiconductor memory
10/14/2003US6633966 FIFO memory having reduced scale
10/14/2003US6633933 Controller for ATAPI mode operation and ATAPI driven universal serial bus mode operation and methods for making the same
10/09/2003WO2003083642A2 A data processing system and method for performing a mathematical operation on multi bit binary integer numbers using floating point arithmetic
10/09/2003WO2002023476A3 Signal processing apparatus
10/09/2003US20030191896 Data-cache data-path
10/09/2003US20030191895 Buffer controller and management method thereof
10/07/2003US6631455 Logic for initializing the depth of the queue pointer memory
10/07/2003US6631389 Apparatus for performing packed shift operations
10/02/2003US20030187902 Associative processor addition and subtraction
10/02/2003US20030187896 In-place associative processor arithmetic
10/01/2003EP1256237B1 Improvements in or relating to data compression
09/2003
09/30/2003US6629258 Variable speed data access control circuit with exponential length wait cycle
09/30/2003US6629226 Fifo read interface protocol
09/30/2003US6629168 Byte-swapping for efficient use of memory
09/30/2003US6629115 Method and apparatus for manipulating vectored data
09/30/2003US6628140 Programmable logic devices with function-specific blocks
09/25/2003WO2002101938A3 Method and circuit for transmitting data from a system which is operated by means of a first clock pulse to a system which is operated by means of a second clock pulse
09/25/2003US20030182504 Method, system, and program for processing input/output (I/O) requests to a storage space having a plurality of storage devices
09/24/2003EP1347355A1 Frequency converter for interconnect buses
09/23/2003US6625711 Method and/or architecture for implementing queue expansion in multiqueue devices
09/23/2003US6625675 Processor for determining physical lane skew order
09/23/2003US6625672 Divided buffer
09/23/2003US6624777 Fast A/D conversion signal processor, RF receiver circuit, digital receiver front end circuit, MRI apparatus, and fast A/D conversion device
09/18/2003WO2003077504A2 Accessory control interface
09/18/2003CA2476981A1 Accessory control interface
09/17/2003EP1344124A1 Method and a commmunication apparatus in a communication system
09/17/2003EP1277112B1 Capturing of a register value to another clock domain
09/16/2003US6622242 System and method for performing generalized operations in connection with bits units of a data word
09/16/2003US6622205 Process for the secure writing of a pointer for a circular memory
09/16/2003US6622198 Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture
09/16/2003US6621225 Intelligent electrical switching devices
09/11/2003US20030172249 Methods of performing DSP operations with complex data type operands
09/11/2003US20030172242 Self-synchronous FIFO memory device having high access efficiency, and system provided with interface for data transfer using the same
09/11/2003US20030172241 High speed, low current consumption FIFO circuit
09/11/2003US20030172206 Pushback fifo
09/11/2003US20030169644 Transferring data between different clock domains
09/10/2003CN1441566A Communication device using three step communication buffer storage
09/04/2003WO2003073296A2 Shared queue for multiple input-streams
09/04/2003WO2003073290A1 Pipelined parallel programming operation in a non-volatile memory system
09/04/2003US20030165277 Data processing system,and data processing method
09/04/2003US20030164836 Method and apparatus for resetting a gray code counter
08/2003
08/28/2003WO2002021285A3 Intermediate buffer control for improving throughput of split transaction interconnect
08/28/2003US20030163660 Dynamically adjustable load-sharing circular queues
08/28/2003US20030163629 Pipelined parallel programming operation in a non-volatile memory system
08/28/2003US20030163618 Shared queue for multiple input-streams
08/28/2003US20030163607 Communication device using three-step communication buffers
08/27/2003EP1339022A2 Data compression system and data restoration system
08/27/2003EP0772809B1 Method for performing a "rotate through carry" operation
08/27/2003CN1438557A Method for setting pixel clock pulse of display driving circuit
08/27/2003CN1119745C Method of emulating shift register using RAM
08/26/2003US6611884 Self-adjusting elasticity data buffer with preload value
08/21/2003US20030159079 Synchronous semiconductor device
08/21/2003US20030159000 Device for interfacing asynchronous data using first-in-first-out
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