| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 01/09/2002 | EP0960512B1 Apparatus and method for synthesizing management packets for transmission between a network switch and a host controller |
| 01/09/2002 | CN1330853A Intelligent electric installation |
| 01/08/2002 | US6338102 Efficient data transfer mechanism for input/output devices having a device driver generating a descriptor queue and monitoring a status queue |
| 01/08/2002 | US6337893 Non-power-of-two grey-code counter system having binary incrementer with counts distributed with bilateral symmetry |
| 01/03/2002 | US20020002671 Parallel processing of multiple data values within a data word |
| 01/02/2002 | EP1168845A1 Video server system |
| 01/02/2002 | EP1168623A1 Digital microelectronic circutit with a clocked data processing unit and a data conversion unit |
| 01/02/2002 | EP1166210A1 Elastic interface apparatus and method therefor |
| 01/01/2002 | US6336181 Microcomputer having built-in serial input-output circuit |
| 12/27/2001 | US20010056451 Parallel processing of multiple data values within a data word |
| 12/27/2001 | US20010055232 Serial access memory and data write/read method |
| 12/25/2001 | US6334163 Elastic interface apparatus and method therefor |
| 12/25/2001 | US6334162 Efficient data transfer mechanism for input/out devices having a device driver generating a descriptor queue and monitoring a status queue |
| 12/25/2001 | US6334153 Passing a communication control block from host to a local device such that a message is processed on the device |
| 12/25/2001 | US6333708 Data acquisition system comprising a circuit for converting a high-frequency analog input signal into a plurality of digital signals |
| 12/20/2001 | US20010054121 Method and circuit for controlling a first-in-first-out (fifo) buffer using a bank of fifo address registers capturing and saving beginning and ending write-pointer addresses |
| 12/20/2001 | DE10124351A1 Self time-controlled transmission system has coder of first and second data sets, processor processing data sets successively in self time-controlled manner and decoder of processed data sets |
| 12/20/2001 | DE10028369A1 Circuit for routing input signal to parallel circuit branches has queue function and clock-delayed reproduction of output signal |
| 12/19/2001 | EP1163569A1 Method and circuit for receiving dual edge clocked data |
| 12/13/2001 | WO2001095123A1 System and method for accessing, organizing, and presenting data |
| 12/13/2001 | WO2001095089A2 Low latency fifo circuits for mixed asynchronous and synchronous systems |
| 12/13/2001 | WO2001095088A1 Converting, and presenting the source document in a target format |
| 12/13/2001 | US20010052055 Active window management for reorder buffer |
| 12/13/2001 | US20010050856 Semiconductor device, module including the semiconductor device, and system including the module |
| 12/13/2001 | CA2412438A1 Low latency fifo circuits for mixed asynchronous and synchronous systems |
| 12/11/2001 | US6329858 Control method and control system for signal transmission |
| 12/06/2001 | WO2001093051A1 Data processing system, and data processing method |
| 12/06/2001 | US20010049797 Method and apparatus for adjusting data delay |
| 12/06/2001 | US20010049757 Programmable task scheduler for use with multiport xDSL processing system |
| 12/06/2001 | US20010049756 Transport convergence sub-system with shared resources for multiport xDSL system |
| 12/04/2001 | US6327651 Wide shifting in the vector permute unit |
| 12/04/2001 | US6327207 Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding |
| 12/04/2001 | US6327196 Synchronous memory device having an adjustable data clocking circuit |
| 11/29/2001 | US20010047465 Mixed hardware/software architecture and method for processing xDSL communications |
| 11/29/2001 | US20010047446 Quantized queue length arbiter |
| 11/29/2001 | US20010047437 FIFO type data input/output apparatus and FIFO type data input/output method |
| 11/29/2001 | US20010047434 xDSL communications systems using shared/multi-function task blocks |
| 11/29/2001 | US20010047433 Obtaining a destination address so that a network interface device can write network data without headers directly into host memory |
| 11/27/2001 | US6324625 Rotating rationed buffer refresh |
| 11/27/2001 | US6324601 Data structure and method for managing multiple ordered sets |
| 11/27/2001 | US6324239 Method and apparatus for a 1 of 4 shifter |
| 11/22/2001 | US20010044805 Synchronization system application object interface |
| 11/22/2001 | US20010043746 Apparatus and method of generating compressed data |
| 11/21/2001 | EP0960505B1 Method and apparatus for controlling initiation of transmission of data as a function of received data |
| 11/21/2001 | EP0847551A4 A set of instructions for operating on packed data |
| 11/21/2001 | EP0786112B1 A circuit for coordinating the timing of operations of asynchronously operating sub-circuits |
| 11/20/2001 | US6321280 System LSI having communication function |
| 11/20/2001 | US6320590 Data bus compressing apparatus |
| 11/20/2001 | US6320522 Encoding and decoding apparatus with matching length detection means for symbol strings |
| 11/15/2001 | WO2001086449A2 System and method for jitter compensation in data transfers |
| 11/15/2001 | US20010042219 Technique for pipelining synchronization to maintain throughput across two asynchronous clock domain boundaries |
| 11/15/2001 | US20010042156 Data generation circuit and method for data generating |
| 11/14/2001 | EP1154574A2 Method for compressing data using trend information |
| 11/14/2001 | EP1154349A2 Method and device for processing measurement data |
| 11/13/2001 | US6317842 Method and circuit for receiving dual edge clocked data |
| 11/13/2001 | US6317806 Static queue and index queue for storing values identifying static queue locations |
| 11/13/2001 | US6317763 Circuits, barrel shifters, and methods of manipulating a bit pattern |
| 11/13/2001 | US6317114 Method and apparatus for image stabilization in display device |
| 11/08/2001 | US20010038715 Compression process for storing trend and characteristics of information in a computer, dummy picture compression signal, data compression means, method for compressing datand method for reproduced data |
| 11/08/2001 | US20010038348 Endian conversion apparatus and an endian conversion method in which a trouble is never induced in a recognition at a plural-byte unit without any delay in an endian process |
| 11/07/2001 | EP1152327A2 Reconfigurable FIFO interface to support multiple channels in bundled agent configurations |
| 11/07/2001 | CN1320865A Data transmission controlling device and electronic apparatus |
| 11/07/2001 | CN1074633C Adaptive bit stream demultiplexing apparatus in decoding system |
| 11/07/2001 | CN1074560C Fifo buffer system having error detection and correction unit |
| 11/06/2001 | US6314478 System for accessing a space appended to a circular queue after traversing an end of the queue and upon completion copying data back to the queue |
| 11/06/2001 | US6314442 Floating-point arithmetic unit which specifies a least significant bit to be incremented |
| 11/06/2001 | US6314156 Space-efficient multi-cycle barrel shifter circuit |
| 11/06/2001 | US6314154 Non-power-of-two Gray-code counter and binary incrementer therefor |
| 11/01/2001 | WO2001082081A2 Capturing of a register value to another clock domain |
| 11/01/2001 | WO2001082053A2 A low latency fifo circuit for mixed clock systems |
| 11/01/2001 | US20010037471 System and method for internal operation of multiple-port xDSL communications systems |
| 11/01/2001 | US20010037443 Logical pipeline for data communications system |
| 11/01/2001 | US20010037397 Intelligent network interface system and method for accelerated protocol processing |
| 11/01/2001 | CA2407407A1 A low latency fifo circuit for mixed clock systems |
| 10/31/2001 | EP1150450A2 Synchronizer |
| 10/31/2001 | EP1150214A1 Endian conversion of plural-byte units without delay |
| 10/31/2001 | EP1149482A1 Synchronizing method and apparatus |
| 10/31/2001 | EP1149472A1 Gray-code counter having a binary incrementer and method of operating the same |
| 10/31/2001 | DE10108379A1 Method for aligning data in tracks carrying packets of data characters, requires transmission of data packets as successive data characters separated by intermediate packet gaps of a number of different first and second blanks |
| 10/31/2001 | CN1320238A High freuqency pipeline decoupling queue design |
| 10/31/2001 | CN1319797A Idempotent unit for data process system |
| 10/30/2001 | US6311239 Architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media |
| 10/30/2001 | US6311199 Sign extension unit |
| 10/30/2001 | CA2130473C Methods and apparatus for retiming and realignment of sts-1 signals into sts-3 type signal |
| 10/25/2001 | WO2001079987A1 Two clock domain pulse to pulse synchronizer |
| 10/24/2001 | CN1319202A Method and device for writing and reading buffer memory |
| 10/24/2001 | CN1318833A Data source, device related to the same, receiving method, medium and information set |
| 10/23/2001 | US6308229 System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic |
| 10/23/2001 | US6308189 Apparatus for partial logical shifts and method therefor |
| 10/18/2001 | US20010032322 High-speed data buffer |
| 10/18/2001 | US20010032302 Methods and apparatus for byte alignment operations for a memory device that stores an odd number of bytes |
| 10/18/2001 | US20010031096 Reversible DCT for lossless - lossy compression |
| 10/17/2001 | CN2454818Y Finger mark, picture anti-fake store-box |
| 10/16/2001 | US6304956 Using two barrel shifters to implement shift, rotate, rotate with carry, and shift double as specified by the X86 architecture |
| 10/16/2001 | US6304936 One-to-many bus bridge using independently and simultaneously selectable logical FIFOS |
| 10/16/2001 | US6304924 Two lock-free, constant-space, multiple-(impure)-reader, single-writer structures |
| 10/11/2001 | US20010029558 First-in first-out data transfer control device having a plurality of banks |
| 10/11/2001 | US20010029539 Computer system, computer, extension unit and interface circuit |
| 10/11/2001 | US20010028353 Method and system for buffer management |
| 10/04/2001 | WO2000038063A9 Method and system for memory allocation in a multiprocessing environment |