| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 10/04/2001 | US20010027540 Apparatus and method for detecting operation value using lookup-table |
| 10/04/2001 | US20010027496 Passing a communication control block to a local device such that a message is processed on the device |
| 10/04/2001 | EP1139227A2 Bus emulation apparatus |
| 10/02/2001 | US6298364 Digital signal processing operation apparatus that allows combined operation |
| 10/02/2001 | US6297760 Data acquisition system comprising real-time analysis and storing means |
| 09/27/2001 | WO2001071482A1 Dual clock domain read fifo |
| 09/27/2001 | US20010025228 Method for evaluating measured data |
| 09/26/2001 | EP1012700B1 Multiple parallel identical finite state machines which share combinatorial logic |
| 09/20/2001 | US20010023462 Information processing system |
| 09/20/2001 | US20010023460 Passing a communication control block from host to a local device such that a message is processed on the device |
| 09/20/2001 | US20010023424 Exponent unit of data processing system |
| 09/19/2001 | EP1133719A1 Automatic detection of 8b/10b data rates |
| 09/18/2001 | US6292873 Dual-ported electronic random access memory that does not introduce additional wait states and that does not cause retransmission of data during shared access |
| 09/13/2001 | US20010021953 Data processing circuit |
| 09/13/2001 | US20010021949 Network interface device employing a DMA command queue |
| 09/13/2001 | US20010020951 Apparatus and method for transferring video data |
| 09/12/2001 | EP1132811A2 FIFO Type data input/output apparatus and FIFO type data input/output method |
| 09/12/2001 | EP0616744B1 Digital clock dejitter circuits for regenerating clock signals with minimal jitter |
| 09/11/2001 | US6289468 Technique for controlling system bus timing with on-chip programmable delay lines |
| 09/11/2001 | US6289427 Controlling a read address or a write address based on the quantity of data read from or written into a memory |
| 09/11/2001 | US6289421 Intelligent memory devices for transferring data between electronic devices |
| 09/11/2001 | US6289366 Speedy shift apparatus for use in arithmetic unit |
| 09/11/2001 | US6289066 Method and apparatus for recentering an elasticity FIFO when receiving 1000BASE-X traffic using minimal information |
| 09/11/2001 | US6289065 FIFO status indicator |
| 09/11/2001 | US6288589 Method and apparatus for generating clock signals |
| 09/07/2001 | WO2001065774A1 Scaleable architecture for multiple-port, system-on-chip adsl communications systems |
| 09/07/2001 | WO2001004724A9 A partitioned shift right logic circuit having rounding support |
| 08/30/2001 | US20010018734 FIFO overflow management |
| 08/30/2001 | US20010018730 Synchronization control apparatus and method |
| 08/30/2001 | DE10053065A1 Vorrichtung und Verfahren für adaptive Jitterpuffer Apparatus and method for adaptive jitter buffer |
| 08/23/2001 | US20010016885 Interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface |
| 08/23/2001 | US20010016861 Apparatus for performing packed shift operations |
| 08/22/2001 | CN1309805A Method and apparatus for decoding |
| 08/21/2001 | US6279055 Data output device and data output method |
| 08/21/2001 | US6279044 Network interface for changing byte alignment transferring on a host bus according to master and slave mode memory and I/O mapping requests |
| 08/21/2001 | US6279010 Method and apparatus for forensic analysis of information stored in computer-readable media |
| 08/16/2001 | US20010014925 Bus emulation apparatus |
| 08/16/2001 | EP1124179A1 An apparatus for signal synchronization between two clock domains |
| 08/15/2001 | CN1308282A Bus simulator |
| 08/14/2001 | US6275896 Data transfer apparatus and method of the same and data input and output controlling apparatus and method of same |
| 08/14/2001 | US6275834 Apparatus for performing packed shift operations |
| 08/09/2001 | WO2001058168A1 Improvements in or relating to data compression |
| 08/09/2001 | WO2001004724A3 A partitioned shift right logic circuit having rounding support |
| 08/09/2001 | US20010013092 Memory latency compensation |
| 08/09/2001 | US20010012290 Data input circuit and semiconductor device utilizing data input circuit |
| 08/09/2001 | CA2399206A1 Improvements in or relating to data compression |
| 08/08/2001 | CN1307275A Geometric series method |
| 08/07/2001 | US6272566 System for maintaining proper buffering within video play list |
| 08/07/2001 | US6272564 Efficient data transfer mechanism for input/output devices |
| 08/02/2001 | WO2001055834A1 Method and apparatus for increasing the battery life of portable electronic devices |
| 08/02/2001 | US20010011334 Memory device |
| 08/01/2001 | EP1120018A2 Intelligent electrical devices |
| 08/01/2001 | EP1119805A1 Endian transformation |
| 07/31/2001 | US6269451 Method and apparatus for adjusting data timing by delaying clock signal |
| 07/31/2001 | US6269413 System with multiple dynamically-sized logical FIFOs sharing single memory and with read/write pointers independently selectable and simultaneously responsive to respective read/write FIFO selections |
| 07/31/2001 | US6269136 Digital differential analyzer data synchronizer |
| 07/31/2001 | US6268746 Method and apparatus for logic synchronization |
| 07/26/2001 | WO2001053943A2 Double-ended queue with concurrent non-blocking insert and remove operations |
| 07/26/2001 | WO2001053942A2 Double-ended queue with concurrent non-blocking insert and remove operations |
| 07/26/2001 | US20010009385 Delay device having a delay lock loop and method of calibration thereof |
| 07/24/2001 | US6266758 Alignment and ordering of vector elements for single instruction multiple data processing |
| 07/24/2001 | US6266748 Priority encoding for FIFO memory devices that interface multiple ports to a data receiving device |
| 07/24/2001 | US6266746 Control apparatus for random access memories |
| 07/19/2001 | US20010009010 Data split parallel shifter and parallel adder/subtractor |
| 07/18/2001 | EP1116098A1 Method and device for writing and reading a buffer memory |
| 07/17/2001 | US6263413 Memory integrated circuit and main memory and graphics memory systems applying the above |
| 07/17/2001 | US6263410 Apparatus and method for asynchronous dual port FIFO |
| 07/17/2001 | US6263408 Method and apparatus for implementing automatic cache variable update |
| 07/11/2001 | CN1303566A Memory management in receiver/decoder |
| 07/11/2001 | CN1303200A Method of controlling time mark bias and equipment for transmitting packet by using said method |
| 07/11/2001 | CN1303053A Queue supervisor of buffer |
| 07/10/2001 | US6260153 Automatic compensation circuit for no margin input data |
| 07/10/2001 | US6260152 Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains |
| 07/10/2001 | US6260055 Data split parallel shifter and parallel adder/subtractor |
| 07/10/2001 | US6260031 Code compaction by evolutionary algorithm |
| 07/10/2001 | US6259650 Dual port memory control signals with synchronized read and write pointers |
| 07/04/2001 | CA2328268A1 Queue manager for a buffer |
| 06/28/2001 | WO2001046988A2 Method and apparatus for routing 1 of n signals |
| 06/28/2001 | WO2000038063A3 Method and system for memory allocation in a multiprocessing environment |
| 06/28/2001 | US20010005879 Inter-device coupler |
| 06/26/2001 | US6252815 First in first out memory circuit |
| 06/26/2001 | US6252425 Method and apparatus for an N-NARY logic circuit |
| 06/26/2001 | US6250821 Method and apparatus for processing branch instructions in an instruction buffer |
| 06/20/2001 | EP1108242A1 Fifo using asynchronous logic |
| 06/19/2001 | US6249875 Interface circuit using plurality of synchronizers for synchronizing respective control signals over a multi-clock environment |
| 06/19/2001 | US6249756 Hybrid flow control |
| 06/19/2001 | US6249280 Media composition system with enhanced user interface features |
| 06/19/2001 | US6249089 Intelligent electrical device comprising microchip |
| 06/14/2001 | WO2001043287A1 Method and apparatus for an n-nary logic circuit |
| 06/14/2001 | US20010003820 Extending the data word length for data transmission and data processing cross-reference to related application |
| 06/13/2001 | EP1107106A2 Delay line for recirculating ALU output data to its input |
| 06/13/2001 | EP1107105A1 Extending the data word length for data transmission and data processing |
| 06/12/2001 | US6247120 Instruction buffer for issuing instruction sets to an instruction decoder |
| 06/12/2001 | US6247112 Bit manipulation instructions |
| 06/12/2001 | US6247072 Real-time data rate matching across a medium |
| 06/12/2001 | US6247060 Passing a communication control block from host to a local device such that a message is processed on the device |
| 06/12/2001 | US6246726 High speed digital data transmission by separately clocking and recombining interleaved data subgroups |
| 06/12/2001 | US6246257 FIFO circuit |
| 06/12/2001 | US6246256 Quantized queue length arbiter |
| 06/05/2001 | US6243846 Forward error correction system for packet based data and real time media, using cross-wise parity calculation |