| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 10/03/2002 | US20020140457 Clocking scheme for ASIC |
| 10/01/2002 | US6460095 Data transfer apparatus, data transfer system and recording medium |
| 09/26/2002 | US20020138685 Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture |
| 09/26/2002 | US20020138675 Processor for determining physical lane skew order |
| 09/26/2002 | US20020138539 Method and apparatus to calculate the difference of two numbers |
| 09/24/2002 | US6457121 Method and apparatus for reordering data in X86 ordering |
| 09/24/2002 | US6457036 System for accurately performing an integer multiply-divide operation |
| 09/24/2002 | CA2353435C Automatic detection of 8b/10b data rates |
| 09/19/2002 | US20020133730 Data bit-to-clock alignment circuit with first bit capture capability |
| 09/19/2002 | US20020133647 Watermark for additional data burst into buffer memory |
| 09/18/2002 | CN1369776A Method for regulating character frequency |
| 09/12/2002 | WO2002071249A2 Method and devices for treating and/or processing data |
| 09/12/2002 | WO2002071196A2 Methods and devices for treating and processing data |
| 09/12/2002 | US20020129324 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip |
| 09/12/2002 | US20020129196 Dual clock domain read fifo |
| 09/12/2002 | US20020129168 Data transfer scheme using caching and differential compression techniques for reducing network load |
| 09/12/2002 | US20020129077 High speed low power 4-2 compressor |
| 09/12/2002 | US20020126123 Method of buffer management and task scheduling for two-dimensional data transforming |
| 09/12/2002 | US20020126095 Multi-mode input control device |
| 09/11/2002 | EP0820612B1 Apparatus and method for peripheral device control with integrated data compression |
| 09/10/2002 | US6449681 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers |
| 09/10/2002 | US6449281 Interface control of communication between a control processor and a digital signal processor |
| 09/06/2002 | WO2002069500A1 Method and apparatus for analog and digital signal and data compression |
| 09/05/2002 | US20020124039 Modulo addressing |
| 09/04/2002 | EP1236278A1 Method and apparatus for an n-nary logic circuit |
| 09/04/2002 | EP0960373B1 Method and apparatus for maintaining a time order by physical ordering in a memory |
| 09/04/2002 | EP0854425B1 Device and method for increasing data security with circular buffer |
| 09/04/2002 | CN1367491A Integrated circuit storage equipment with multiport ultrahigh speed buffer storage array and its operation method |
| 09/03/2002 | US6445825 Apparatus and method of generating compressed data |
| 09/03/2002 | US6445700 Serial communication circuit |
| 09/03/2002 | US6445635 High speed asynchronous and programmable state machine for generating almost empty synchronous flags in a synchronous FIFO |
| 09/03/2002 | US6445634 Serial access memory and data write/read method |
| 08/29/2002 | US20020120828 Bit field manipulation |
| 08/29/2002 | US20020120796 Maintaining remote queue using two counters in transfer controller with hub and ports |
| 08/29/2002 | US20020118126 Methods and apparatus for constant-weight encoding & decoding |
| 08/28/2002 | EP1234228A1 Processor with improved accuracy for multiply-add operations |
| 08/27/2002 | US6442657 Flag generation scheme for FIFOs |
| 08/27/2002 | US6442646 First-in-first-out (FIFO) memory device for inputting/outputting data with variable lengths |
| 08/27/2002 | US6442627 Output FIFO data transfer control device |
| 08/27/2002 | US6441917 Buffer memory managing method and printing apparatus using the method |
| 08/22/2002 | US20020116556 Apparatus and method for generating FIFO fullness indicator signals |
| 08/20/2002 | US6438703 Method and system for selectively varying signal delay in response to detection of a quiescent signal |
| 08/20/2002 | US6438610 System using buffers for decompressing compressed scanner image data received from a network peripheral device and transmitting to a client's web browser |
| 08/20/2002 | US6438102 Method and apparatus for providing asynchronous memory functions for bi-directional traffic in a switch platform |
| 08/20/2002 | US6437715 Decimal to binary coder/decoder |
| 08/15/2002 | WO2002063776A2 Method for compressing/decompressing a structured document |
| 08/15/2002 | WO2002063461A1 Method and system for buffering streamed data |
| 08/15/2002 | CA2435936A1 Method and system for buffering of streamed media |
| 08/14/2002 | EP1231716A2 Decimal to binary coder/decoder |
| 08/14/2002 | DE10202758A1 DMA-Controller sowie Verfahren und Computersystem mit einem solchen DMA controller and method and computer system with such a |
| 08/13/2002 | US6434684 Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same |
| 08/13/2002 | US6434676 FIFO with random re-read support and its application |
| 08/13/2002 | US6434655 Fast access to buffer circuits |
| 08/13/2002 | US6434642 FIFO memory system and method with improved determination of full and empty conditions and amount of data stored |
| 08/13/2002 | US6434640 Unload counter adjust logic for a receiver buffer |
| 08/08/2002 | WO2002019535A9 Hardware implementation of a compression algorithm |
| 08/08/2002 | US20020108070 Bus clock controlling apparatus and method |
| 08/08/2002 | US20020108069 Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
| 08/08/2002 | US20020105951 Playback of streamed media |
| 08/07/2002 | EP1229437A1 Multirate circular buffer and method of operating the same |
| 08/01/2002 | WO2002060226A1 Communication port control module for lighting systems |
| 07/31/2002 | EP1010053B1 Interface circuit for full-custom and semi-custom timing domains |
| 07/30/2002 | US6427173 Intelligent network interfaced device and system for accelerated communication |
| 07/25/2002 | WO2002057891A1 Data bit-to-clock alignment circuit with first bit capture capability |
| 07/25/2002 | US20020099451 Communication port control module for lighting systems |
| 07/24/2002 | CN1360241A Bus clock controlling device and method for portable computer |
| 07/23/2002 | US6425088 Method of the apparatus for transferring data between circuits |
| 07/23/2002 | US6424688 Method to transfer data in a system with multiple clock domains using clock skipping techniques |
| 07/23/2002 | US6424189 Apparatus and system for multi-stage event synchronization |
| 07/18/2002 | WO2002056478A1 Data compression method with identifier of regressive string reference |
| 07/18/2002 | WO2001086449A3 System and method for jitter compensation in data transfers |
| 07/17/2002 | CN1359493A Process for the secure writing of a pointer for a circular memory |
| 07/17/2002 | CN1359486A Generating optimized computer data field conversion routines |
| 07/17/2002 | CN1359067A Method for making data in circular buffer effective |
| 07/16/2002 | US6421784 Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element |
| 07/16/2002 | US6421770 Buffer memory configuration having a memory between a USB and a CPU |
| 07/16/2002 | US6420921 Delay signal generating apparatus and semiconductor test apparatus |
| 07/16/2002 | US6420901 Quantized queue length arbiter |
| 07/11/2002 | WO2002054227A1 Modulo addressing |
| 07/11/2002 | US20020091886 Data compression method and system that use a regressive string reference, pointing to and delimiting an encoded pointee string, and identify the reference through a signalling element, an encoding device and a decoding device arranged for implementing the method, and a storage medium provided with information produced by such encoding device and/or arranged for decoding by such decoding device |
| 07/11/2002 | US20020091878 Multi-function apparatus and method for receiving and printing electronic letter |
| 07/11/2002 | US20020091844 Network interface device that fast-path processes solicited session layer read commands |
| 07/11/2002 | US20020089359 Phase selection mechanism for optimal sampling of source synchronous clocking interface data |
| 07/10/2002 | EP1221647A1 Virtual insertion of cells from a secondary source into a fifo |
| 07/04/2002 | WO2002052399A1 Method and a commmunication apparatus in a communication system |
| 07/04/2002 | US20020087758 Dynamic buffer size allocation for multiplexed streaming |
| 07/04/2002 | US20020087756 Virtual insertion of cells from a secondary source into a FIFO |
| 07/04/2002 | US20020087755 Data synchronization interface |
| 07/04/2002 | US20020087732 Transmit fast-path processing on TCP/IP offload network interface device |
| 07/04/2002 | US20020085575 Interface control of communication between a control processor and a digital signal processor |
| 07/04/2002 | US20020085489 Variable codec frame length |
| 07/04/2002 | US20020084807 Asynchronous FIFO circuit and method of reading and writing data through asynchronous FIFO circuit |
| 07/03/2002 | EP1220086A2 Shift circuits and partial sticky bit detection for floating point calculation |
| 07/02/2002 | US6415365 Write buffer for use in a data processing apparatus |
| 07/02/2002 | US6414700 System for accessing a large number of menu items using a zoned menu bar |
| 07/02/2002 | US6414609 Data width conversion apparatus and data processing apparatus |
| 06/27/2002 | WO2002050656A2 Apparatus and method for generating fifo fullness indicator signals |
| 06/27/2002 | WO2002050655A2 Fifo buffer with output rate adjusting |
| 06/27/2002 | US20020083289 Circuit and method for controlling buffers in semiconductor memory device |
| 06/27/2002 | US20020083106 Dynamic popcount/shift circuit |