Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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07/15/1997 | US5649074 Raster image data compression method and system |
07/15/1997 | US5648777 Data converter with FIFO |
07/15/1997 | US5648773 Data compression transmission system |
07/08/1997 | US5646906 Method & Apparatus for real-time processing of moving picture signals using flash memories |
07/08/1997 | US5646873 Barrel shifter device and variable-length decoder |
07/03/1997 | DE19651775A1 Buffer memory control for separation of sequential sample data in audio decoder |
07/01/1997 | US5644387 High-speed data register for laser range finders |
06/25/1997 | EP0780846A2 Field programmable memory array |
06/25/1997 | EP0780761A2 Method and apparatus for instruction prefetching in a graphics processor |
06/18/1997 | EP0779575A1 Output synchronization method and apparatus |
06/18/1997 | CN1152244A Data processing device including buffer memory |
06/17/1997 | US5640601 Apparatus and method for indexing frames as the images are being compressed using signal from data digitizer to notify host unit at every frame |
06/17/1997 | US5640515 FIFO buffer system having enhanced controllability |
06/17/1997 | US5640366 Sequential -access asynchronous memory device and corresponding process for storage and reading |
06/17/1997 | US5640158 Method of data compression |
06/17/1997 | US5640105 Current mode null convention threshold gate |
06/10/1997 | US5638535 Method and apparatus for providing flow control with lying for input/output operations in a computer system |
06/10/1997 | US5638503 Method and apparatus for generating bitmaps from outlines containing bezier curves |
06/10/1997 | US5638490 Fuzzy logic data processor |
06/04/1997 | EP0417314B1 Serial in to parallel out converting circuit |
06/03/1997 | US5636224 Method and apparatus for interleave/de-interleave addressing in data communication circuits |
06/03/1997 | US5635931 System and method for compressing data information |
05/27/1997 | US5634065 Data processing apparatus |
05/27/1997 | US5634015 Generic high bandwidth adapter providing data communications between diverse communication networks and computer system |
05/27/1997 | US5633878 Self-diagnostic data buffers |
05/27/1997 | US5633819 Inexact leading-one/leading-zero prediction integrated with a floating-point adder |
05/27/1997 | US5633634 Data rate conversion circuit |
05/21/1997 | EP0359809B1 Apparatus and method for floating point normalization prediction |
05/21/1997 | CN1150309A Method and circuit arrangement for resynchronization of memory management arrangement |
05/20/1997 | US5632024 Microcomputer executing compressed program and generating compressed branch addresses |
05/15/1997 | WO1997017809A1 Digital coding |
05/14/1997 | EP0773689A1 Video data processing device comprising a buffer memory |
05/14/1997 | EP0772860A1 Display controller capable of accessing graphics data from a shared system memory |
05/14/1997 | EP0772810A1 Non-arithmetical circular buffer cell availability status indicator circuit |
05/14/1997 | EP0772809A1 Method for performing a "rotate through carry" operation |
05/14/1997 | EP0772808A1 Barrel shifter |
05/13/1997 | US5630100 Simulating multi-phase clock designs using a single clock edge based system |
05/13/1997 | US5630091 For use with a computer storage device |
05/07/1997 | EP0772121A1 Method and apparatus for memory sequencing |
05/06/1997 | US5627797 Full and empty flag generator for synchronous FIFOS |
05/06/1997 | US5627774 Parallel calculation of exponent and sticky bit during normalization |
05/06/1997 | US5627773 Floating point unit data path alignment |
05/06/1997 | US5627533 Adjusting encoding table size and memory allocation for data compression in response to input data |
05/02/1997 | EP0770292A1 Two stage clock dejitter circuit for regenerating an e4 telecommunications signal from the data component of an sts-3c signal |
04/29/1997 | US5625465 Information processing methodology |
04/27/1997 | CA2182422A1 Method and apparatus for memory sequencing |
04/24/1997 | WO1997008620A3 Data processing system comprising an asynchronously controlled pipeline |
04/24/1997 | DE19623465A1 Floating point normalisation circuit |
04/22/1997 | US5623699 Read only linear stream based cache system |
04/22/1997 | US5623621 Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer |
04/22/1997 | US5623608 Method and apparatus for adaptive circular predictive buffer management |
04/22/1997 | US5623607 Data transfer control method for controlling transfer of data through a buffer without causing the buffer to become empty or overflow |
04/22/1997 | US5623449 Flag detection for first-in-first-out memories |
04/16/1997 | EP0768600A1 Locked exchange Fifo |
04/16/1997 | CN1147676A First-in first-out memory |
04/10/1997 | WO1997013326A1 A serial data interface apparatus and method for detecting an input word length and selecting an operating mode accordingly |
04/08/1997 | US5619653 Buffer device with resender |
04/03/1997 | DE19622045A1 Data compressor using search tree |
04/02/1997 | EP0669021B1 Multi-lingual computer programs |
04/01/1997 | US5617543 Non-arithmetical circular buffer cell availability status indicator circuit |
04/01/1997 | US5617118 Mode dependent minimum FIFO fill level controls processor access to video memory |
03/30/1997 | CA2176056A1 Data rate conversion circuit |
03/25/1997 | US5614899 Apparatus and method for compressing texts |
03/19/1997 | CN1145702A Device and method for encoding data and device and method for decoding data |
03/18/1997 | US5612926 Sequential access memory |
03/18/1997 | US5612693 Sliding window data compression using a toroidal bit shift register |
03/12/1997 | EP0762283A1 Flag detection for first-in first-out memories |
03/06/1997 | WO1997008620A2 Data processing system comprising an asynchronously controlled pipeline |
03/06/1997 | WO1997008610A1 An apparatus for performing multiply-add operations on packed data |
03/06/1997 | WO1997008608A1 A set of instructions for operating on packed data |
03/05/1997 | EP0760501A1 Data handling system with circular queue formed in paged memory |
02/27/1997 | DE4290392C2 Clock rate matching for independent networks |
02/26/1997 | EP0759663A1 Device and method for encoding data and device and method for decoding data |
02/25/1997 | US5606359 Video on demand system with multiple data sources configured to provide vcr-like services |
02/19/1997 | EP0758770A1 Method and circuit for memory control resynchronization |
02/19/1997 | CN1143219A Bit length changeable data process circuit and method |
02/18/1997 | US5604497 Apparatus and method for increasing density of run length limited block codes without increasing error propagation |
02/18/1997 | US5604495 Data compression method and system |
02/12/1997 | EP0758123A2 Block normalization processor |
02/11/1997 | US5602995 Method and apparatus for buffering data within stations of a communication network with mapping of packet numbers to buffer's physical addresses |
02/11/1997 | US5602780 Serial to parallel and parallel to serial architecture for a RAM based FIFO memory |
02/11/1997 | US5602537 Technique for eliminating data transmit memory underruns |
02/04/1997 | US5600826 Structured data processor for converting between sequential and tree structured data |
02/04/1997 | US5600815 High density buffer memory architecture |
01/29/1997 | CN1141538A Variable-length code encoding and segmenting apparatus having byte alignment unit |
01/28/1997 | US5598580 High performance channel adapter having a pass through function |
01/28/1997 | US5598552 Error free data transfers |
01/28/1997 | US5598362 Apparatus and method for performing both 24 bit and 16 bit arithmetic |
01/28/1997 | US5598113 Fully asynchronous interface with programmable metastability settling time synchronizer |
01/21/1997 | US5596725 Fifo queue having replaceable entries |
01/21/1997 | US5596724 Input/output data port with a parallel and serial interface |
01/21/1997 | US5596540 Serial to parallel and parallel to serial architecture for a RAM based FIFO memory |
01/14/1997 | US5594702 Multi-first-in-first-out memory circuit |
01/14/1997 | US5594700 Sequential memory |
01/14/1997 | US5594437 Circuit and method of unpacking a serial bitstream |
01/09/1997 | WO1997001140A1 A circuit for coordinating the timing of operations of asynchronously operating sub-circuits |
01/08/1997 | EP0752664A2 Method and apparatus for reporting data transfer between hardware and software |
01/08/1997 | EP0752651A2 Index value reference for shared data structures |
01/08/1997 | EP0752642A1 Method and apparatus for dynamically calculating degrees of fullness of a synchronous fifo |
01/08/1997 | CN1139861A Length changeable code and segment and device |