| Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116) |
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| 03/27/2002 | EP1191740A2 Methods and apparatus for hardware normalization and denormalization |
| 03/27/2002 | EP1191696A2 Programmable logic devices with function-specific blocks |
| 03/27/2002 | EP1190324A1 Process for the secure writing of a pointer for a circular memory |
| 03/26/2002 | US6363476 Multiply-add operating device for floating point number |
| 03/26/2002 | US6363470 Circular buffer management |
| 03/26/2002 | US6363441 Timing controller having dependency memory, selection serialization component and reordering component for maintaining time dependencies in conversions between sequential and parallel operations using staging memory |
| 03/26/2002 | US6363132 Asynchronous data conversion system for enabling error to be prevented |
| 03/21/2002 | WO2002023476A2 Signal processing apparatus |
| 03/21/2002 | WO2002023326A1 Handler for floating-point denormalized numbers |
| 03/21/2002 | WO2002003745A3 Technique for implementing fractional interval times for fine granularity bandwidth allocation |
| 03/21/2002 | US20020035663 Method of validating data in circular buffers |
| 03/21/2002 | US20020035440 System and method for calibrating control unit |
| 03/21/2002 | US20020034273 System and method for clock synchronization for USB sink device |
| 03/21/2002 | US20020034195 Method for compensating for clock signal difference between a switch and a peripheral device, and associated apparatus |
| 03/21/2002 | US20020034162 Technique for implementing fractional interval times for fine granularity bandwidth allocation |
| 03/20/2002 | EP1188162A1 Data transfer apparatus, data transfer system, and data transfer method with double buffering |
| 03/20/2002 | EP1188108A1 Two clock domain pulse to pulse synchronizer |
| 03/19/2002 | US6360286 Sequential data transfer with common clock signal for receiver and sequential storage device and with slack register storing overflow item when set-up time is insufficient |
| 03/14/2002 | WO2002021848A1 Method for compressing/decompressing structured documents |
| 03/14/2002 | WO2002021285A2 Intermediate buffer control for improving throughput of split transaction interconnect |
| 03/14/2002 | US20020032830 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers |
| 03/14/2002 | US20020032817 Bus control system |
| 03/14/2002 | US20020031148 Clock producing circuit and semiconductor integrated circuit for communication |
| 03/13/2002 | EP1186999A2 Method and apparatus for maintaining a linked list |
| 03/13/2002 | EP1186994A2 Input data processing circuit |
| 03/12/2002 | US6356962 Network device and method of controlling flow of data arranged in frames in a data-based network |
| 03/12/2002 | US6356611 Bit rate control interface for the recording and/or reading of digital data |
| 03/07/2002 | WO2002019535A1 Hardware implementation of a compression algorithm |
| 03/07/2002 | WO2002019093A1 Method and apparatus for flexible data types |
| 03/07/2002 | US20020029356 Input data processing circuit |
| 03/07/2002 | US20020029306 System LSI having communication function |
| 03/07/2002 | US20020029227 Management server for synchronization system |
| 03/07/2002 | US20020029206 Data compressing apparatus and a data decompressing apparatus, a data compressing method and a data decompressing method,and a data compressing or decompressing dictionary creating apparatus and a computer readable recording medium storing a data compressing |
| 03/07/2002 | US20020027909 Multientity queue pointer chain technique |
| 03/06/2002 | EP1185013A2 System and method for clock synchronization for USB sink device |
| 03/06/2002 | EP1183596A1 Generating optimized computer data field conversion routines |
| 03/06/2002 | EP1183584A2 Fft processor with overflow prevention |
| 03/06/2002 | EP1073950B1 Method and apparatus for performing shift operations on packed data |
| 03/05/2002 | US6353864 System LSI having communication function |
| 03/05/2002 | US6353829 Method and system for memory allocation in a multiprocessing environment |
| 02/28/2002 | WO2002017494A2 Non-power-of-two grey-code counter system having binary incrementer with counts distributed with bilateral symmetry |
| 02/28/2002 | US20020026461 System and method for creating a source document and presenting the source document to a user in a target format |
| 02/28/2002 | US20020024526 Processing of a data set |
| 02/28/2002 | US20020024514 Data bus compressing apparatus |
| 02/27/2002 | EP1182543A1 Maintaining remote queue using two counters in transfer controller with hub and ports |
| 02/27/2002 | EP1181639A1 Apparatus and method for providing a cyclic buffer |
| 02/26/2002 | US6351793 Memory latency compensation |
| 02/26/2002 | US6351758 Bit and digit reversal methods |
| 02/26/2002 | US6351725 Interface apparatus |
| 02/21/2002 | WO2002014992A1 System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system |
| 02/21/2002 | US20020023238 Fifo memory control circuit |
| 02/21/2002 | DE10035965A1 Data stream output method for MPEG decoder of digital TV receiver, involves changing frequency of clock signal used for reading-out data from FIFO memory, based on its storage level |
| 02/20/2002 | CN1336602A Processor for data set |
| 02/19/2002 | US6348881 Efficient hardware implementation of a compression algorithm |
| 02/14/2002 | US20020019952 Method of determining data transfer speed in data transfer apparatus |
| 02/14/2002 | US20020019841 Data processing device having a central processing unit and digital signal processing unit |
| 02/14/2002 | US20020019671 Asynchronous controller generation method |
| 02/13/2002 | EP1029264B1 Remote control system which minimizes screen refresh time by selecting compression algorithm |
| 02/12/2002 | US6347348 Buffer management system having an output control configured to retrieve data in response to a retrieval request from a requesting one of a plurality of destinations |
| 02/12/2002 | US6346836 Synchronizing stage |
| 02/12/2002 | CA2307816C Buffering data that flows between buses operating at different frequencies |
| 02/07/2002 | US20020016850 Method and device for parameter independent buffer underrun prevention |
| 02/07/2002 | US20020016178 Communication system for transferring large data from network interface to radio interface |
| 02/07/2002 | DE10102887A1 Verzögerungsvorrichtung, die eine Verzögerungssperrschleife aufweist und Verfahren zum Kalibrieren derselben Delay means having a delay lock loop and method of calibrating same |
| 02/06/2002 | EP1178687A1 Processing data packets having valid and some non-valid data items |
| 02/06/2002 | EP1178396A1 Apparatus and method for the normalisation of data |
| 02/06/2002 | CN1334661A System and method for clock synchronization of general serial bus receiver apparatus |
| 02/05/2002 | US6345008 Fast reprogrammable FIFO status flags system |
| 01/31/2002 | WO2002008917A1 Queuing architecture and method for scheduling disk access requests |
| 01/31/2002 | US20020013875 Elastic interface apparatus and method therefor |
| 01/31/2002 | US20020013864 Queuing architecture including a plurality of queues and assocated method for controlling admission for disk access requests for video content |
| 01/31/2002 | US20020013821 Method and network device for creating buffer structures in shared memory |
| 01/30/2002 | CN1333495A Hidden safety cipher |
| 01/30/2002 | CN1078720C First-in first-out memory device for emabling sizes of input-output data to be different from each other and method therefor |
| 01/29/2002 | US6343337 Wide shifting in the vector permute unit |
| 01/29/2002 | US6343303 Method of determining a scaling factor |
| 01/24/2002 | US20020010849 Data object architecture and method for xDSL ASIC processor |
| 01/24/2002 | US20020010810 xDSL function ASIC processor & method of operation |
| 01/24/2002 | US20020010807 Data package including synchronization data |
| 01/24/2002 | US20020009236 Image data conversion device and image data conversion method for converting the order of pixels |
| 01/24/2002 | US20020009235 Reversible dct for lossless - lossy compression |
| 01/24/2002 | US20020008554 Apparatus and method for tracking between data and echo clock |
| 01/24/2002 | US20020008256 Scaleable architecture for multiple-port, system-on-chip ADSL communications systems |
| 01/23/2002 | EP1174790A1 Method and apparatus for determining the number of empty memory locations in a FIFO memory device |
| 01/23/2002 | CN1332416A Method and device for maintenance of chained list |
| 01/22/2002 | US6341323 Information processing system |
| 01/22/2002 | US6341313 Flow controlling method and apparatus for network between processors |
| 01/22/2002 | US6341096 Semiconductor memory device |
| 01/17/2002 | US20020006225 Encoding apparatus, decoding apparatus, encoding/decoding apparatus, encoding method and decoding method |
| 01/17/2002 | US20020005792 Coding apparatus and decoding apparatus |
| 01/15/2002 | US6339809 Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers |
| 01/15/2002 | US6339558 FIFO memory device and FIFO control method |
| 01/15/2002 | CA2076466C Method for buffering high bandwidth data from an input device |
| 01/10/2002 | WO2002003745A2 Technique for implementing fractional interval times for fine granularity bandwidth allocation |
| 01/10/2002 | WO2002003629A2 Connection shaping control technique implemented over a data network |
| 01/10/2002 | WO2002003612A2 Technique for assigning schedule resources to multiple ports in correct proportions |
| 01/10/2002 | WO2002003206A2 Multientity queue pointer chain tehnique |
| 01/10/2002 | US20020004871 xDSL symbol processor & method of operating same |
| 01/10/2002 | DE10031632A1 Digital signal sequence generator for audio analyzer reads out repeatedly next data block from ring buffer only when repeated read out of previous data block is interrupted |
| 01/10/2002 | DE10031222A1 Digitale mikroelektronische Schaltung mit einer getakteten Datenverarbeitungseinheit und einer Umwandlungseinheit Digital microelectronic circuit having a clocked data processing unit and a conversion unit |