Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled
Patents for G06F 5 - Methods or arrangements for data conversion without changing the order or content of the data handled (8,116)
01/2000
01/12/2000EP0847552A4 An apparatus for performing multiply-add operations on packed data
01/11/2000US6014727 Method and system for buffering messages in an efficient but largely undivided manner
01/05/2000EP0969356A2 System and method for managing buffers using free pointer FIFOs containing pointers to empty buffers
12/1999
12/29/1999WO1999067788A1 Semiconductor memory device
12/28/1999US6009451 Method for generating barrel shifter result flags directly from input data
12/28/1999US6009263 Emulating agent and method for reformatting computer instructions into a standard uniform format
12/28/1999US6009107 Data transmission system
12/23/1999WO1999066392A1 An interface apparatus for connecting devices operating at different clock rates, and a method of operating the interface
12/22/1999EP0965129A1 Recursive multi-channel interface
12/21/1999US6006340 Communication interface between two finite state machines operating at different clock domains
12/21/1999US6006244 Circuit for shifting or rotating operands of multiple size
12/21/1999US6005504 Position information encoding apparatus and method thereof, position information decoding apparatus and method thereof, and map information processing apparatus and method thereof
12/21/1999US6005422 Semiconductor integrated circuit and consumed power reducing method
12/21/1999CA2152474C Interface apparatus
12/16/1999WO1999065026A2 Transferring compressed audio via a playback buffer
12/14/1999US6003099 Arrangement and method relating to handling of digital signals and a processing arrangement comprising such
12/14/1999US6002625 Cell array and sense amplifier structure exhibiting improved noise characteristic and reduced size
12/14/1999US6002283 Apparatus for generating an asynchronous status flag with defined minimum pulse
12/14/1999CA2007168C Variable length string matcher
12/08/1999EP0962855A1 Fast acces to buffer circuits
12/08/1999EP0962077A1 Integrated multiport switch having management information base (mib) interface temporary storage
12/08/1999EP0680636B1 Interface apparatus
12/07/1999US6000037 Method and apparatus for synchronizing data transfer
12/07/1999US5999960 Block-normalization in multiply-add floating point sequence without wait cycles
12/07/1999US5999478 Highly integrated tri-port memory buffers having fast fall-through capability and methods of operating same
12/07/1999US5999458 Latch circuit, data output circuit and semiconductor device having the circuits
12/02/1999DE19853688C1 Method of transferring data between computers
12/01/1999EP0960536A2 Queuing structure and method for prioritization of frames in a network switch
12/01/1999EP0960512A1 Apparatus and method for synthesizing management packets for transmission between a network switch and a host controller
12/01/1999EP0960511A1 Method and apparatus for reclaiming buffers
12/01/1999EP0960510A1 Split-queue architecture and method of queuing
12/01/1999EP0960505A1 Method and apparatus for controlling initiation of transmission of data as a function of received data
12/01/1999EP0960504A1 Multicopy queue structure with searchable cache area
12/01/1999EP0960502A1 Method and apparatus for transmitting multiple copies by replicating data identifiers
12/01/1999EP0960373A1 Method and apparatus for maintaining a time order by physical ordering in a memory
12/01/1999EP0852037B1 Unicode converter
11/1999
11/30/1999US5995748 Three input arithmetic logic unit with shifter and/or mask generator
11/30/1999US5995747 Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator
11/30/1999US5995579 Barrel shifter, circuit and method of manipulating a bit pattern
11/30/1999US5994920 Half-full flag generator for synchronous FIFOs
11/25/1999WO1999060496A1 Circuit and method for calibrating phase shift between a plurality of digitizers in a data acquisition system
11/25/1999WO1999060495A1 Data acquisition system comprising means for analysing and storing in real time
11/25/1999WO1999060494A1 Data acquisition system comprising an analog input signal conversion circuit
11/25/1999WO1999060475A1 A leading bit anticipator for floating point multiplication
11/24/1999EP0958587A2 Recompression server
11/23/1999US5991834 State machine design for generating half-full and half-empty flags in an asynchronous FIFO
11/23/1999US5991786 Circuit and method for shifting or rotating operands of multiple size
11/23/1999US5990813 Method and apparatus for synchronizing external data to an internal timing signal
11/23/1999US5990811 Transfer clock converter for digital data
11/20/1999CA2272194A1 Method of determining a scaling factor
11/18/1999WO1999059279A1 Variable codec frame length
11/18/1999WO1999059069A1 Cache memory for two-dimensional data fields
11/18/1999DE19920469A1 Hardware bit coder for data to be transmitted
11/16/1999US5987603 Apparatus and method for reversing bits using a shifter
11/16/1999US5987507 Multi-port communication network device including common buffer memory with threshold control of port packet counters
11/16/1999US5987083 Signal transmission apparatus with a plurality of LSIS
11/16/1999US5987081 Method and apparatus for a testable high frequency synchronizer
11/11/1999DE19819863A1 Circuit operating on the FIFO principle
11/09/1999US5983333 High speed module address generator
11/09/1999US5983305 Network adapter with data aligner
11/09/1999US5983293 File system for dividing buffer areas into different block sizes for system and user data
11/09/1999US5982397 Video graphics controller having locked and unlocked modes of operation
11/09/1999US5982307 Code translation circuit for converting a binary data to a binary coded decimal data
11/09/1999CA2132762C Method and apparatus for data compression
11/04/1999WO1999056457A2 Portable data transmission system for global and local computer networks
11/03/1999EP0953976A1 Information processing method and apparatus, automovive information system and method of controlling the same, and storage medium on which an information processing programm is stored
11/02/1999US5978957 Very fast pipelined shifter element with parity prediction
11/02/1999US5978868 System for generating buffer status flags by comparing read and write pointers and determining direction of progression of read pointer with respect to write pointer
11/02/1999US5978822 Circuit for rotating, left shifting, or right shifting bits
11/02/1999US5978810 Data management system and method for storing a long record in a set of shorter keyed records
10/1999
10/28/1999WO1999055000A2 Differential receiver using a delay lock loop to compensate skew
10/28/1999WO1999054812A1 Method and apparatus for performing shift operations on packed data
10/28/1999CA2329233A1 Skew-insensitive low voltage differential receiver
10/26/1999US5974539 Three input arithmetic logic unit with shifter and mask generator
10/26/1999US5974516 Byte-writable two-dimensional FIFO buffer having storage locations with fields indicating storage location availability and data ordering
10/26/1999US5974485 Arrangement and method for improving the data integrity with a ring buffer
10/26/1999US5974483 Multiple transparent access to in put peripherals
10/26/1999US5974482 Single port first-in-first-out (FIFO) device having overwrite protection and diagnostic capabilities
10/26/1999US5974102 Synchronizing circuit
10/19/1999US5968180 Data capture circuit for asynchronous data transfer
10/19/1999US5968149 Tandem operation of input/output data compression modules
10/14/1999DE19903841A1 Flußsteuerungsverfahren und -vorrichtung für Netzwerk zwischen Prozessoren Flußsteuerungsverfahren and apparatus for network between processors
10/14/1999DE19815961A1 Elektronische Schaltung zur Mehrkanalverarbeitung von Grundfunktionen An electronic circuit for multi-channel processing of basic functions
10/13/1999EP0949808A2 PID filter circuit and FIFO circuit
10/13/1999EP0949773A2 Electronic circuit for multichannel processing of elementary functions
10/13/1999EP0949589A2 Data compression by use of prime exponents
10/09/1999CA2267598A1 Electronic circuit for multichannel processing of basic functions
10/07/1999WO1999051021A1 Memory management in a receiver/decoder
10/07/1999WO1999050741A1 Device and method for buffer protection
10/07/1999CA2324086A1 Memory management in a receiver/decoder
10/05/1999US5963499 Cascadable multi-channel network memory with dynamic allocation
10/05/1999US5963056 To generate output flags representing the status of a fifo buffer
10/05/1999US5961649 Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio
10/05/1999US5961635 Three input arithmetic logic unit with barrel rotator and mask generator
10/05/1999US5961615 Method and apparatus for queuing data
10/05/1999US5961575 Microprocessor having combined shift and rotate circuit
09/1999
09/30/1999DE19812917A1 Asynchronous FIFO memory
09/29/1999EP0946053A1 Memory management in a receiver/decoder
09/29/1999EP0945776A2 Data transfer circuit for semiconductor integrated circuit
09/29/1999CN1229952A Data transfer circuit for semiconductor integrated circuit
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