| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/28/1999 | EP0931329A1 Rf plasma etch reactor with internal inductive coil antenna and electrically conductive chamber walls |
| 07/28/1999 | EP0931288A1 Layout for a semiconductor memory device having redundant elements |
| 07/28/1999 | EP0931234A1 Method and apparatus for providing a purified resource |
| 07/28/1999 | EP0931187A1 A METHOD FOR PRODUCING A REGION DOPED WITH BORON IN A SiC-LAYER |
| 07/28/1999 | EP0931175A1 Conveyor and delivery device |
| 07/28/1999 | EP0931118A1 Composition and method for polishing a composite comprising titanium |
| 07/28/1999 | EP0930978A1 Composition and method for polishing a composite |
| 07/28/1999 | EP0930974A1 Inverted stamping process |
| 07/28/1999 | EP0930943A1 Curing polymer layers on semiconductor substrates using variable frequency microwave energy |
| 07/28/1999 | EP0852617A4 Apparatus and methods for active programmable matrix devices |
| 07/28/1999 | EP0834190A4 Method for shallow junction formation |
| 07/28/1999 | EP0830642B1 Film-stripping process |
| 07/28/1999 | EP0792572B1 An apparatus for generation of a linear arc discharge for plasma processing |
| 07/28/1999 | CN2331084Y Element for supporting semiconductor chip in non-contact chip card |
| 07/28/1999 | CN2331083Y Temperature-control semi-conductor photoelectric characteristic testing sample stand |
| 07/28/1999 | CN2331082Y Microwave transistor metallized wiring strengthening structure |
| 07/28/1999 | CN1224532A Interelectrode connecting structure, interelectrode connecting method, semiconductor device, semiconductor mounting method, liquid crystal display, and electronic equipment |
| 07/28/1999 | CN1224513A Photomask blanks |
| 07/28/1999 | CN1224328A Magnetic shield apparatus |
| 07/28/1999 | CN1224278A High frequency clock signal distribution utilizing CMOS negative impedance terminations |
| 07/28/1999 | CN1224243A CMOS static random access memory devices |
| 07/28/1999 | CN1224241A Lead-on-chip type semiconductor device having thin plate and method for manufacturing the same |
| 07/28/1999 | CN1224239A Semiconductor device with low permittivity interlayer insulating film and method of manufacturing the same |
| 07/28/1999 | CN1224238A Adhesive sheet |
| 07/28/1999 | CN1224237A Work transfer method and system |
| 07/28/1999 | CN1224236A Method and apparatus for quantifying proximity effect by measuring device performance |
| 07/28/1999 | CN1224235A Anisotropic dry etching method |
| 07/28/1999 | CN1224234A Method for etching silicon layer |
| 07/28/1999 | CN1224233A Multi-phase mask |
| 07/28/1999 | CN1224219A Input buffer circuit for semiconductor IC circuit |
| 07/28/1999 | CN1224187A 微型计算机 Microcomputers |
| 07/28/1999 | CN1224183A Method for controlling states of units of equipment in semiconductor fabricating equipment controlling system |
| 07/28/1999 | CN1224085A Superhigh vacuum chemical vapor phase deposition epitoxy system |
| 07/28/1999 | CN1224077A Process for etching diamond film pattern with reactive ion beam |
| 07/28/1999 | CN1224073A Method for forming PZT thin film using seed layer |
| 07/28/1999 | CN1044412C Source voltage control circuit |
| 07/27/1999 | US5930677 Method of fabricating an integrated circuit device |
| 07/27/1999 | US5930676 Multilayered interconnection substrate and process for fabricating the same |
| 07/27/1999 | US5930675 Process of forming inter-level connection without increase of contact resistance |
| 07/27/1999 | US5930674 Semiconductor device with improved planarization properties |
| 07/27/1999 | US5930673 Method for forming a metal contact |
| 07/27/1999 | US5930672 Manufacture of semiconductor device having reliable and fine connection hole |
| 07/27/1999 | US5930671 CVD titanium silicide for contract hole plugs |
| 07/27/1999 | US5930670 Method of forming a tungsten plug of a semiconductor device |
| 07/27/1999 | US5930669 Continuous highly conductive metal wiring structures and method for fabricating the same |
| 07/27/1999 | US5930667 Method for fabricating multilevel interconnection structure for semiconductor devices |
| 07/27/1999 | US5930666 Method of making a semiconductor device |
| 07/27/1999 | US5930664 Process for preventing corrosion of aluminum bonding pads after passivation/ARC layer etching |
| 07/27/1999 | US5930663 Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
| 07/27/1999 | US5930662 Method of making ohmic contact between a thin film polysilicon layer and a subsequently provided conductive layer and integrated circuitry |
| 07/27/1999 | US5930661 Substrate clamp design for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers |
| 07/27/1999 | US5930660 Method for fabricating diode with improved reverse energy characteristics |
| 07/27/1999 | US5930659 Forming minimal size spaces in integrated circuit conductive lines |
| 07/27/1999 | US5930658 Covering defects in gate region of semiconductor substrate with conformal layer of silicon oxide-free oxygen-doped silicon, final oxidation forms quality uniform silicon oxide coating |
| 07/27/1999 | US5930657 Method of depositing an amorphous silicon film by APCVD |
| 07/27/1999 | US5930656 Forming dielectric passivation film over mixed metal nitride layer on substrate within same chemical reactor without contamination or oxidation; simplification |
| 07/27/1999 | US5930655 Defluorination of surface region of barrier layer by exposure to ozone plasma prior to printing circuit pattern of metal conductors |
| 07/27/1999 | US5930654 Method of producing semiconductor devices including a step of dicing a semiconductor wafer while covering the semiconductor wafer by a tape |
| 07/27/1999 | US5930653 Method of manufacturing a semiconductor device for surface mounting suitable for comparatively high voltages, and such a semiconductor device |
| 07/27/1999 | US5930652 Semiconductor encapsulation method |
| 07/27/1999 | US5930651 Method of forming a semiconductor device having a plurality of cavity defined gating regions |
| 07/27/1999 | US5930650 Method of etching silicon materials |
| 07/27/1999 | US5930649 Stress relieving, nondeforming, oxidation resistance |
| 07/27/1999 | US5930648 Semiconductor memory device having different substrate thickness between memory cell area and peripheral area and manufacturing method thereof |
| 07/27/1999 | US5930647 Methods of forming field oxide and active area regions on a semiconductive substrate |
| 07/27/1999 | US5930646 Conversion of polysilicon layer to novel second dielectric layer to compensate for stress caused by densification of first dielectric layer in shallow trench |
| 07/27/1999 | US5930645 Shallow trench isolation formation with reduced polish stop thickness |
| 07/27/1999 | US5930644 Method of forming a shallow trench isolation using oxide slope etching |
| 07/27/1999 | US5930643 Silicon on insulator (soi) formed by oxidation of stable subsurface defects surrounded by amorphous region upon oxygen diffusion into the region |
| 07/27/1999 | US5930642 Transistor with buried insulative layer beneath the channel region |
| 07/27/1999 | US5930641 Method for forming an integrated circuit container having partially rugged surface |
| 07/27/1999 | US5930640 Mechanical supports for very thin stacked capacitor plates |
| 07/27/1999 | US5930639 Forming capacitor by selectively etching deposited first electrode layer through patterned hard metal nitride mask, removing mask, depositing capacitor dielectric layer thereon and forming second electrode in same manner as first |
| 07/27/1999 | US5930638 Method of making a low parasitic resistor on ultrathin silicon on insulator |
| 07/27/1999 | US5930637 On a semiconductor wafer for integrated circuits |
| 07/27/1999 | US5930636 Method of fabricating high-frequency GaAs substrate-based Schottky barrier diodes |
| 07/27/1999 | US5930635 Complementary Si/SiGe heterojunction bipolar technology |
| 07/27/1999 | US5930634 Method of making an IGFET with a multilevel gate |
| 07/27/1999 | US5930633 Integrated butt-contact process in shallow trench isolation |
| 07/27/1999 | US5930632 Forming thin film of cobalt niobate dielectric and electroconductive cobalt silicide electrode layer for high speed transistor performance |
| 07/27/1999 | US5930631 Method of making double-poly MONOS flash EEPROM cell |
| 07/27/1999 | US5930630 Method for device ruggedness improvement and on-resistance reduction for power MOSFET achieved by novel source contact structure |
| 07/27/1999 | US5930629 Semiconductor memory device and method of manufacturing the same |
| 07/27/1999 | US5930628 Method for fabricating one time programmable read only memory |
| 07/27/1999 | US5930627 Process improvements in self-aligned polysilicon MOSFET technology using silicon oxynitride |
| 07/27/1999 | US5930626 Method of fabricating capacitor of memory cell |
| 07/27/1999 | US5930625 Method for fabricating a stacked, or crown shaped, capacitor structure |
| 07/27/1999 | US5930624 Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring |
| 07/27/1999 | US5930623 Deposition of silicon-nitride sidewall and polysilicon sidewall spacers in openings formed in oxide layers to allow subsequently formed contact window to be narrowed to prevent etching damage to bit line/electrode structures |
| 07/27/1999 | US5930622 Method for forming a DRAM cell with a double-crown shaped capacitor |
| 07/27/1999 | US5930621 Methods for forming vertical electrode structures and related structures |
| 07/27/1999 | US5930620 Semiconductor process |
| 07/27/1999 | US5930619 Method of making trench EPROM simultaneously with forming a DRAM cell |
| 07/27/1999 | US5930618 Method of Making High-K Dielectrics for embedded DRAMS |
| 07/27/1999 | US5930617 Method of forming deep sub-micron CMOS transistors with self-aligned silicided contact and extended S/D junction |
| 07/27/1999 | US5930616 Methods of forming a field effect transistor and method of forming CMOS circuitry |
| 07/27/1999 | US5930615 Method of forming CMOS having simultaneous formation of halo regions of PMOS and part of source/drain of NMOS |
| 07/27/1999 | US5930614 Method for forming MOS device having field shield isolation |
| 07/27/1999 | US5930613 Method of making EPROM in high density CMOS having metallization capacitor |
| 07/27/1999 | US5930612 Method of manufacturing complementary MOS semiconductor device |