Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2000
06/27/2000US6081382 Catadioptric reduction projection optical system
06/27/2000US6081334 Endpoint detection for semiconductor processes
06/27/2000US6081320 Illumination apparatus and exposure apparatus
06/27/2000US6081319 Illumination system and scan type exposure apparatus
06/27/2000US6081308 Method for manufacturing liquid crystal display
06/27/2000US6081272 Merging dummy structure representations for improved distribution of artifacts in a semiconductor layer
06/27/2000US6081145 Semiconductor integrated circuit device
06/27/2000US6081142 Hold time margin increased semiconductor device and access time adjusting method for same
06/27/2000US6081127 Method and arrangement for the response analysis of semiconductor materials with optical excitation
06/27/2000US6081110 Thermal isolation plate for probe card
06/27/2000US6081072 Filament lamp for wafer heating and heating light source
06/27/2000US6081041 Static random access memory cell having vertically arranged drive transistors to improve the packing density and data stabilization in the cell
06/27/2000US6081040 Semiconductor device having alignment mark
06/27/2000US6081038 Semiconductor chip package structure
06/27/2000US6081037 Semiconductor component having a semiconductor chip mounted to a chip mount
06/27/2000US6081036 Semiconductor device
06/27/2000US6081034 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer
06/27/2000US6081032 Dual damascene multi-level metallization and interconnection structure
06/27/2000US6081029 Resin encapsulated semiconductor device having a reduced thickness and improved reliability
06/27/2000US6081027 Integrated heat sink
06/27/2000US6081024 TAB tape semiconductor device
06/27/2000US6081023 Semiconductor device
06/27/2000US6081021 Conductor-insulator-conductor structure
06/27/2000US6081018 Solid state image sensor
06/27/2000US6081016 CMOS device with improved wiring density
06/27/2000US6081014 Silicon carbide chrome thin-film resistor
06/27/2000US6081013 Semiconductor device having a reduced distance between the input resistor and the internal circuit
06/27/2000US6081012 Semiconductor integrated circuit device
06/27/2000US6081011 CMOS logic gate having buried channel NMOS transistor for semiconductor devices and fabrication method of the same
06/27/2000US6081010 MOS semiconductor device with self-aligned punchthrough stops and method of fabrication
06/27/2000US6081007 Semiconductor device comprising MIS transistor with high concentration channel injection region
06/27/2000US6081005 Semiconductor integrated circuit
06/27/2000US6081004 BiCMOS compacted logic array
06/27/2000US6081003 Heterojunction bipolar transistor with ballast resistor
06/27/2000US6080998 Amorphous silicon germanium thin film and photovoltaic element
06/27/2000US6080995 Quantum device
06/27/2000US6080990 Position measuring apparatus
06/27/2000US6080970 Wafer heating apparatus
06/27/2000US6080969 Apparatus for and method of thermally processing substrate
06/27/2000US6080965 Single-substrate-heat-treatment apparatus in semiconductor processing system
06/27/2000US6080953 Power supply device for electrical discharge machining
06/27/2000US6080931 Semiconductor package
06/27/2000US6080709 Comprising 1) oxalic acid or ammonium oxalate and 2) polyaminocarboxylic acids, but contains no hydrogen fluoride.
06/27/2000US6080683 Reacting a mixture including h2sif6, butylpyridinium chloride, and a fe2+ /fe3+ aqueous reduction-oxidation solution with a semiconductor substrate to form said silicon oxide-based layer.
06/27/2000US6080682 Methodology for achieving dual gate oxide thicknesses
06/27/2000US6080681 Etching process presenting anti-microloading effect by using the resist patterns as an etching mask
06/27/2000US6080680 Method and composition for dry etching in semiconductor fabrication
06/27/2000US6080679 High-speed soft evacuation process and system
06/27/2000US6080678 Aromatic polysulfone film; o2 gas etching the arc film, and so2 gas preventing erosion of the photoresist pattern by forming cs2 on sides of the photoresist pattern
06/27/2000US6080677 Method for preventing micromasking in shallow trench isolation process etching
06/27/2000US6080676 Dry etch process; main flow of gas that includes an argon flow at an argon flow rate and a fluorocarbon flow; applying rf power in the frequency range of 360 to 440 khz
06/27/2000US6080675 Method for cleaning waste matter from the backside of a semiconductor wafer substrate
06/27/2000US6080674 Method for forming via holes
06/27/2000US6080673 Particle coagulation in the polishing slurry is minimized and the microelectronic device experiences minimal damage.
06/27/2000US6080672 Self-aligned contact formation for semiconductor devices
06/27/2000US6080671 Process of chemical-mechanical polishing and manufacturing an integrated circuit
06/27/2000US6080670 Method of detecting a polishing endpoint layer of a semiconductor wafer which includes a non-reactive reporting specie
06/27/2000US6080669 Very high pressure ionized metal deposition technique which results in improved sidewall step coverage with enhanced subsequent filling of the channel or vias by conductive materials.
06/27/2000US6080668 Sequential build-up organic chip carrier and method of manufacture
06/27/2000US6080667 Method of treating CVD titanium nitride with silicon ions
06/27/2000US6080666 Method for increasing landing pad area
06/27/2000US6080665 Integrated nitrogen-treated titanium layer to prevent interaction of titanium and aluminum
06/27/2000US6080664 Method for fabricating a high aspect ratio stacked contact hole
06/27/2000US6080663 Dual damascene
06/27/2000US6080662 Method for forming multi-level contacts using a H-containing fluorocarbon chemistry
06/27/2000US6080661 Methods for fabricating gate and diffusion contacts in self-aligned contact processes
06/27/2000US6080660 Via structure and method of manufacture
06/27/2000US6080659 Method to form an alignment mark
06/27/2000US6080658 Device protection structure for preventing plasma charging damage and vertical cross talk
06/27/2000US6080657 An aluminum layer is sputter deposited over a titanium oxynitride layer at a high temperature and a low power
06/27/2000US6080656 Method for forming a self-aligned copper structure with improved planarity
06/27/2000US6080655 Method for fabricating conductive components in microelectronic devices and substrate structures thereof
06/27/2000US6080654 Simplified method of forming self-aligned vias in a semiconductor device
06/27/2000US6080653 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component
06/27/2000US6080652 Method of fabricating a semiconductor device having a multi-layered wiring
06/27/2000US6080651 Wire bonding method
06/27/2000US6080650 Method and apparatus for attaching particles to a substrate
06/27/2000US6080649 Fusible link in an integrated semiconductor circuit and process for producing the fusible link
06/27/2000US6080648 Insulated gate field effect transistor using a salicide (self-aligned silicidation) technology.
06/27/2000US6080647 Process to form a trench-free buried contact
06/27/2000US6080646 Method of fabricating a metal-oxide-semiconductor transistor with a metal gate
06/27/2000US6080645 Method of making a doped silicon diffusion barrier region
06/27/2000US6080644 Complementary bipolar/CMOS epitaxial structure and process
06/27/2000US6080643 Vapor deposition; laser annealing; doping; patterning
06/27/2000US6080642 Method of manufacturing a semiconductor device and a device for applying such a method
06/27/2000US6080641 Method of manufacturing semiconductor wafer
06/27/2000US6080640 High density integrated circuits
06/27/2000US6080639 Semiconductor device containing P-HDP interdielectric layer
06/27/2000US6080638 Formation of thin spacer at corner of shallow trench isolation (STI)
06/27/2000US6080637 Shallow trench isolation technology to eliminate a kink effect
06/27/2000US6080635 Method of photo alignment for shallow trench isolation with chemical mechanical polishing
06/27/2000US6080634 Method of mending and testing semiconductor apparatus
06/27/2000US6080633 Method for manufacturing capacitor's lower electrode
06/27/2000US6080631 Method for manufacturing self-alignment type bipolar transistor having epitaxial base layer
06/27/2000US6080630 Method for forming a MOS device with self-compensating VT -implants
06/27/2000US6080629 Ion implantation into a gate electrode layer using an implant profile displacement layer
06/27/2000US6080628 Method of forming shallow trench isolation for integrated circuit applications
06/27/2000US6080627 Method for forming a trench power metal-oxide semiconductor transistor
06/27/2000US6080626 Memory cell for EEPROM devices, and corresponding fabricating process
06/27/2000US6080625 Method for making dual-polysilicon structures in integrated circuits
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