| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/11/2000 | US6087718 Stacking type semiconductor chip package |
| 07/11/2000 | US6087717 Semiconductor device and manufacturing method |
| 07/11/2000 | US6087716 Semiconductor device package having a connection substrate with turned back leads and method thereof |
| 07/11/2000 | US6087715 Semiconductor device, and manufacturing method of the same |
| 07/11/2000 | US6087710 Semiconductor device having self-aligned contacts |
| 07/11/2000 | US6087709 Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby |
| 07/11/2000 | US6087708 Semiconductor integrated circuit device and a method of producing the same |
| 07/11/2000 | US6087706 Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls |
| 07/11/2000 | US6087705 Trench isolation structure partially bound between a pair of low K dielectric structures |
| 07/11/2000 | US6087704 Structure and method for manufacturing group III-V composite Schottky contacts enhanced by a sulphur fluoride/phosphorus fluoride layer |
| 07/11/2000 | US6087702 Rare-earth schottky diode structure |
| 07/11/2000 | US6087700 Gate having a barrier of titanium silicide |
| 07/11/2000 | US6087699 Laminated gate mask ROM device |
| 07/11/2000 | US6087698 Semiconductor device and method of manufacturing the same |
| 07/11/2000 | US6087696 Stacked tunneling dielectric technology for improving data retention of EEPROM cell |
| 07/11/2000 | US6087695 Source side injection flash EEPROM memory cell with dielectric pillar and operation |
| 07/11/2000 | US6087694 Semiconductor memory device and fabrication method thereof |
| 07/11/2000 | US6087693 Semiconductor device with reduced stepped portions |
| 07/11/2000 | US6087692 DRAM cell configuration and method for its fabrication |
| 07/11/2000 | US6087691 Semiconductor device having lower minority carrier noise |
| 07/11/2000 | US6087688 Field effect transistor |
| 07/11/2000 | US6087687 MISFET device with ferroelectric gate insulator |
| 07/11/2000 | US6087684 Bipolar transistor |
| 07/11/2000 | US6087683 Silicon germanium heterostructure bipolar transistor with indium doped base |
| 07/11/2000 | US6087679 Semiconductor thin film and semiconductor device |
| 07/11/2000 | US6087678 Thin-film transistor display devices having composite electrodes |
| 07/11/2000 | US6087675 Semiconductor device with an insulation film having emitter contact windows filled with polysilicon film |
| 07/11/2000 | US6087673 Method of inspecting pattern and apparatus thereof |
| 07/11/2000 | US6087669 Charged-particle-beam projection-microlithography apparatus and transfer methods |
| 07/11/2000 | US6087668 Charged-particle-beam projection method and apparatus |
| 07/11/2000 | US6087667 Charged-particle-beam (CPB) lithography apparatus, evaluation method, and CPB source |
| 07/11/2000 | US6087659 Apparatus and method for secondary electron emission microscope |
| 07/11/2000 | US6087648 Active matrix display device and method of manufacturing the same |
| 07/11/2000 | US6087647 Solid state imaging device and driving method therefor |
| 07/11/2000 | US6087632 Heat processing device with hot plate and associated reflector |
| 07/11/2000 | US6087623 Semiconductor device marking apparatus using a rotating stopper |
| 07/11/2000 | US6087615 Ion source for an ion beam arrangement |
| 07/11/2000 | US6087614 Plasma treating device |
| 07/11/2000 | US6087585 Micro-dimensional coupling conductor |
| 07/11/2000 | US6087580 Semiconductor having large volume fraction of intermediate range order material |
| 07/11/2000 | US6087414 Process for direct substitution of high performance polymers with unsaturated ester groups |
| 07/11/2000 | US6087285 Zirconia sintered body, process for production thereof, and application thereof |
| 07/11/2000 | US6087278 Method for fabricating semiconductor devices having an HDP-CVD oxide layer as a passivation layer |
| 07/11/2000 | US6087276 Method of making a TFT having an ion plated silicon dioxide capping layer |
| 07/11/2000 | US6087275 Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilicate glass |
| 07/11/2000 | US6087273 Making a multilayer semiconductor structure using an etchant solution containing specific percent by volume of phosphoric acid, sulfuric acid, and water |
| 07/11/2000 | US6087272 Method of producing thin film transistor |
| 07/11/2000 | US6087271 Methods for removal of an anti-reflective coating following a resist protect etching process |
| 07/11/2000 | US6087270 Forming a base etch mask layer of electroconductive material such as polypyrrole; patterning a layer of resist over the etch mask layer; reactive ion etching the etch mask layer through opening in resist layer under specified conditions |
| 07/11/2000 | US6087269 Forming aluminum-based layer(al), titanium/titanium nitride layer, tungsten-based layer(w), and patterned photoresist layer; etching w layer using first etchant and photoresist as etch mask, etching al using second etchant and w as etch mask |
| 07/11/2000 | US6087268 Forming gate electrode of boron-doped polysilicon over gate oxide, isotropically forming a nitride over gate electrode at low temperature, anisotropically etching the nitride to leave a nitride sidewall spacer adjacent the gate electrode |
| 07/11/2000 | US6087267 Process for forming an integrated circuit |
| 07/11/2000 | US6087266 Methods and apparatus for improving microloading while etching a substrate |
| 07/11/2000 | US6087265 Method for removing redeposited veils from etched platinum |
| 07/11/2000 | US6087264 Forming a gate silicide on a semiconductor substrate, forming a patterned mask on gate material, etching gate material with a mixture of chlorine and oxygen using mask and increasing bias power as the substrate temperature decreases |
| 07/11/2000 | US6087263 Methods of forming integrated circuitry and integrated circuitry structures |
| 07/11/2000 | US6087262 Method for manufacturing shallow trench isolation structure |
| 07/11/2000 | US6087261 Forming a dielectric film on a semiconductor substrate, in a low pressure atmosphere, adding a low pressure reaction gas for deposition of metal or metal nitride and an oxidizing gas for forming an oxygen containing conductor film |
| 07/11/2000 | US6087260 Method of manufacturing bit line |
| 07/11/2000 | US6087259 Chemical vapor deposition of a titanium nitride film which serves as a diffusion barrier to suppress a reaction of tungsten, which forms the bit line, with silicon on a contact region during a thermal process at a high temperature |
| 07/11/2000 | US6087257 Methods of fabricating a selectively deposited tungsten nitride layer and metal wiring using a tungsten nitride layer |
| 07/11/2000 | US6087256 Method for manufacturing modified T-shaped gate electrode |
| 07/11/2000 | US6087255 Conductive layer with anti-reflective surface portion |
| 07/11/2000 | US6087254 Technique for elimination of pitting on silicon substrate during gate stack etch |
| 07/11/2000 | US6087253 Method of forming landing plugs for PMOS and NMOS |
| 07/11/2000 | US6087252 Dual damascene |
| 07/11/2000 | US6087251 Method of fabricating a dual damascene structure |
| 07/11/2000 | US6087250 Forming silicon oxide(sio2) film on a semiconductor having first metal interconnection(mi), coating sio2 with silicon ladder polymer, pressing to flatten device, heat treating, forming sio2 layer on ladder polymer, then forming second mi |
| 07/11/2000 | US6087249 Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation |
| 07/11/2000 | US6087248 Method of forming a transistor having thin doped semiconductor gate |
| 07/11/2000 | US6087247 Method for forming shallow junctions in semiconductor wafers using controlled, low level oxygen ambients during annealing |
| 07/11/2000 | US6087246 Method for fabricating dual gate semiconductor device |
| 07/11/2000 | US6087245 Method of gettering crystallization catalyst for forming a silicon film |
| 07/11/2000 | US6087244 Methods of forming semiconductor-on-insulator devices including buried layers of opposite conductivity type |
| 07/11/2000 | US6087243 Method of forming trench isolation with high integrity, ultra thin gate oxide |
| 07/11/2000 | US6087242 Optionally forming an oxide cap layer on the silicon surface of the bonded silicon on insulator (soi) structure, then annealing the structure in a slightly oxidizing ambient; detecting bonding defects with laser pulse technique |
| 07/11/2000 | US6087241 Method of forming side dielectrically isolated semiconductor devices and MOS semiconductor devices fabricated by this method |
| 07/11/2000 | US6087240 Method of forming rough polysilicon surfaces suitable for capacitor construction |
| 07/11/2000 | US6087239 Fabricating semiconductors, by forming on the device a disposable spacer comprising a germanium-silicon (ge-si) layer, removing the spacer by oxidizing to form a volatile ge-si oxide, removing remaining nonvolatile oxide with water |
| 07/11/2000 | US6087238 Semiconductor device having reduced-width polysilicon gate and non-oxidizing barrier layer and method of manufacture thereof |
| 07/11/2000 | US6087237 Method of manufacturing a MOSFET by forming a single oxide layer doping with either an oxide accelerator or an oxide inhibitor producing asymmetric thickness |
| 07/11/2000 | US6087236 Forming oxide layer on substrate and converting to oxynitride layer; removing portion of oxynitride layer, forming gate electrode and patterning; forming source/drain terminals |
| 07/11/2000 | US6087235 Method for effective fabrication of a field effect transistor with elevated drain and source contact structures |
| 07/11/2000 | US6087234 Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction |
| 07/11/2000 | US6087233 Forming trench isolators in semiconductor devices |
| 07/11/2000 | US6087232 Forming drift region of second conductivity type in epitaxial layer of first conductivity type having silicon substrate; forming pad oxide, nitride pattern, field oxide, convex region, tapered top layer, tetraethoxy silane oxide pattern |
| 07/11/2000 | US6087231 Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant |
| 07/11/2000 | US6087230 Method of fabricating an SOI device having a channel with variable thickness |
| 07/11/2000 | US6087229 Composite semiconductor gate dielectrics |
| 07/11/2000 | US6087228 Method of making a nonvolatile memory cell using EPROM mask and ROM processing steps |
| 07/11/2000 | US6087226 Methods of forming capacitors including electrodes with hemispherical grained silicon layers on sidewalls thereof and related structures |
| 07/11/2000 | US6087225 Method for dual gate oxide dual workfunction CMOS |
| 07/11/2000 | US6087224 Manufacture of trench-gate semiconductor devices |
| 07/11/2000 | US6087223 Method of fabricating flash memory with dissymmetrical floating gate |
| 07/11/2000 | US6087222 Method of manufacture of vertical split gate flash memory device |
| 07/11/2000 | US6087221 Method of fabricating two dissimilar devices with diminished processing steps |
| 07/11/2000 | US6087220 Stack etch method for flash memory devices |
| 07/11/2000 | US6087219 Highly reliable flash memory structure with halo source |
| 07/11/2000 | US6087218 Method for manufacturing DRAM capacitor |
| 07/11/2000 | US6087217 Method for improving capacitance in DRAM capacitors and devices formed |