Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2000
10/17/2000US6133158 Process for removing alkali metals from solvents used in the manufacture of semiconductor wafers
10/17/2000US6133157 Selectively etching n-type doped second silicon layer over doped first silicon layer with etching gas including freon-14 gas and hydrogen chloride or chlorine
10/17/2000US6133156 Anisotropic etch method
10/17/2000US6133155 Method for preventing corrosion of a metallic layer of a semiconductor chip
10/17/2000US6133153 Self-aligned contacts for semiconductor device
10/17/2000US6133152 Co-rotating edge ring extension for use in a semiconductor processing chamber
10/17/2000US6133151 HDP-CVD method for spacer formation
10/17/2000US6133150 Semiconductor device and method for manufacturing the same
10/17/2000US6133149 Forming a diffusion barrier layer of tungsten nitride between tungsten silicide underlayer on semiconductor substrate and silicon nitride overcoating, then photolithographically forming gate structure
10/17/2000US6133148 Method of depositing film for semiconductor device in single wafer type apparatus using a lamp heating method
10/17/2000US6133147 Process for selective metal deposition in holes of semiconductor device
10/17/2000US6133145 Method to increase the etch rate selectivity between metal and photoresist via use of a plasma treatment
10/17/2000US6133144 Self aligned dual damascene process and structure with low parasitic capacitance
10/17/2000US6133143 Performing a cleaning process without using acetone solution after the patterned photoresist layer is removed, then nucleation and vapor deposition to fill accurately formed via hole
10/17/2000US6133142 Lower metal feature profile with overhanging ARC layer to improve robustness of borderless vias
10/17/2000US6133141 Methods of forming electrical connections between conductive layers
10/17/2000US6133140 Method of manufacturing dual damascene utilizing anisotropic and isotropic properties
10/17/2000US6133139 Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
10/17/2000US6133138 Method of manufacturing semiconductor device having multilayer interconnection structure
10/17/2000US6133137 Semiconductor device and method of manufacturing the same
10/17/2000US6133136 Robust interconnect structure
10/17/2000US6133135 Process for manufacturing electronic circuits
10/17/2000US6133133 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component
10/17/2000US6133132 Method for controlling transistor spacer width
10/17/2000US6133131 Method of forming a gate spacer on a semiconductor wafer
10/17/2000US6133130 Method for fabricating an embedded dynamic random access memory using self-aligned silicide technology
10/17/2000US6133129 Method for fabricating a metal structure with reduced length that is beyond photolithography limitations
10/17/2000US6133128 Method for patterning polysilicon gate layer based on a photodefinable hard mask process
10/17/2000US6133127 Method for manufacturing a semiconductor device
10/17/2000US6133126 Method for fabricating a dopant region
10/17/2000US6133125 Selective area diffusion control process
10/17/2000US6133124 Damaging the crystal structure of a portion of the substrate beneath a spacer and depositing a layer of metal on the substrate, subsequent siliciding allows a portion of silicide layer to extend laterally beneath the spacer
10/17/2000US6133123 Fabrication of semiconductor gettering structures by ion implantation
10/17/2000US6133122 Thermal treatment of semiconductor between the ion injection step forming the diffusion layer and the activation of the diffusion layer, thereby discharging fluorine
10/17/2000US6133121 Apparatus for supporting semiconductor wafers and semiconductor wafer processing method using supporting apparatus
10/17/2000US6133120 Doping boron as charge acceptor to occupy silicon sites in the silicon carbide crystal lattice
10/17/2000US6133119 Photoelectric conversion device and method manufacturing same
10/17/2000US6133118 Edge polysilicon buffer LOCOS isolation
10/17/2000US6133117 Method of forming trench isolation for high voltage device
10/17/2000US6133116 Methods of forming trench isolation regions having conductive shields therein
10/17/2000US6133115 Formation of gate electrode
10/17/2000US6133114 Method for fabricating a shallow trench isolation
10/17/2000US6133113 Method of manufacturing shallow trench isolation
10/17/2000US6133112 Thin film formation process
10/17/2000US6133110 Method of manufacturing a dual cylinder-shaped capacitor
10/17/2000US6133109 Method for manufacturing a DRAM cell capacitor
10/17/2000US6133108 Dielectric etch protection using a pre-patterned via-fill capacitor
10/17/2000US6133106 Fabrication of a planar MOSFET with raised source/drain by chemical mechanical polishing and nitride replacement
10/17/2000US6133105 Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure
10/17/2000US6133104 Method of eliminating buried contact trench in MOSFET devices with self-aligned silicide including a silicon connection to the buried contact region which comprises a doped silicon sidewall
10/17/2000US6133103 Method for fabricating mask ROM
10/17/2000US6133102 Method of fabricating double poly-gate high density multi-state flat mask ROM cells
10/17/2000US6133101 Low mask count process to fabricate mask read only memory devices
10/17/2000US6133100 Method for manufacturing a read only memory array
10/17/2000US6133099 Vertical MOSFET and method of manufacturing thereof
10/17/2000US6133098 Process for making and programming and operating a dual-bit multi-level ballistic flash memory
10/17/2000US6133097 Method for forming mirror image split gate flash memory devices by forming a central source line slot
10/17/2000US6133096 Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices
10/17/2000US6133095 Method for creating diffusion areas for sources and drains without an etch step
10/17/2000US6133094 Semiconductor device and process of producing the same
10/17/2000US6133093 Method for forming an integrated circuit
10/17/2000US6133092 Low temperature process for fabricating layered superlattice materials and making electronic devices including same
10/17/2000US6133091 Method of fabricating a lower electrode of capacitor
10/17/2000US6133090 Method of fabricating cylindrical capacitor
10/17/2000US6133089 Method for fabricating a DRAM capacitor
10/17/2000US6133088 Method of forming crown-shaped capacitor
10/17/2000US6133087 Method of making a DRAM element and a logic element
10/17/2000US6133086 First treating with a remote oxygen plasma or an ultraviolet-ozone treatment, followed by a spike annealing second treatment step to increase the purity and the dielectric constant, prevent current leakage
10/17/2000US6133085 Method for making a DRAM capacitor using a rotated photolithography mask
10/17/2000US6133084 Method of fabricating static random access memory
10/17/2000US6133083 Method to fabricate embedded DRAM
10/17/2000US6133082 Method of fabricating CMOS semiconductor device
10/17/2000US6133081 Method of forming twin well
10/17/2000US6133079 Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions
10/17/2000US6133078 Method for manufacturing a semiconductor device having an ESD protection region
10/17/2000US6133077 Formation of high-voltage and low-voltage devices on a semiconductor substrate
10/17/2000US6133076 Manufacturing method of semiconductor
10/17/2000US6133075 Semiconductor device and method of fabricating the same
10/17/2000US6133074 Thin film transistor and method of fabricating the same
10/17/2000US6133073 Thin film semiconductor and method for manufacturing the same, semiconductor device and method for manufacturing the same
10/17/2000US6133072 Microelectronic connector with planar elastomer sockets
10/17/2000US6133071 Semiconductor device with plate heat sink free from cracks due to thermal stress and process for assembling it with package
10/17/2000US6133070 Circuit member for semiconductor device, semiconductor device using the same, and method for manufacturing them
10/17/2000US6133069 Method of manufacturing the electronic using the anode junction method
10/17/2000US6133067 Architecture for dual-chip integrated circuit package and method of manufacturing the same
10/17/2000US6133066 Semiconductor element mounting method
10/17/2000US6133065 Multi-chip module employing carrier substrate with micromachined alignment structures and method of forming
10/17/2000US6133064 Flip chip ball grid array package with laminated substrate
10/17/2000US6133063 Process for producing a pin layer sequence on a perovskite and a perovskite having a pin layer sequence
10/17/2000US6133060 Method of protecting light sensitive regions of integrated circuits
10/17/2000US6133056 Field emission displays with reduced light leakage
10/17/2000US6133054 Method and apparatus for testing an integrated circuit
10/17/2000US6133052 Bump inspection method
10/17/2000US6133051 Chemical vapor deposition and annealing to transform it into a ferroelectric layer
10/17/2000US6133050 Coating with a liquid precursor containing a plurality of metal moieties, drying by heating and exposing to an ultraviolet radiation to increase the c-axis orientation in metal oxide layered superlattice material thin film
10/17/2000US6132939 Covering a protective film made of a paraffin before or after exposing the chemically amplified resist film by use of a mask
10/17/2000US6132936 Monomer and polymer for photoresist, and photoresist using the same
10/17/2000US6132928 Coating solution for forming antireflective coating film
10/17/2000US6132926 Semiconductors
10/17/2000US6132910 Method of implementing electron beam lithography using uniquely positioned alignment marks and a wafer with such alignment marks
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