| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 03/27/2001 | US6207963 Ion beam implantation using conical magnetic scanning |
| 03/27/2001 | US6207959 Ion implanter |
| 03/27/2001 | US6207937 Temperature control system for a thermal reactor |
| 03/27/2001 | US6207936 Model-based predictive control of thermal processing |
| 03/27/2001 | US6207932 Heater block for heating wafer |
| 03/27/2001 | US6207891 Columnar-grained polycrystalline solar cell substrate |
| 03/27/2001 | US6207890 Photovoltaic element and method for manufacture thereof |
| 03/27/2001 | US6207788 Novolak resin precursor, novolak resin and positive photoresist composition containing the novolak resin |
| 03/27/2001 | US6207787 Antireflective coating for microlithography |
| 03/27/2001 | US6207732 Heat-setting single-component LVA (low-viscosity adhesive) system for bonding in the micro-range |
| 03/27/2001 | US6207630 For cleaning substrates, such as semiconductor-based substrates, as well as processing equipment |
| 03/27/2001 | US6207591 Method and equipment for manufacturing semiconductor device |
| 03/27/2001 | US6207590 Flowing silane into the process chamber; flowing n2o into the process chamber; generating a rf signal at a first predetermined power at a first frequency; and generating a rf signal at a second predetermined power at a second frequency. |
| 03/27/2001 | US6207589 Method of forming a doped metal oxide dielectric film |
| 03/27/2001 | US6207588 Method for simultaneously forming thinner and thicker parts of a dual oxide layer having varying thicknesses |
| 03/27/2001 | US6207587 Method for forming a dielectric |
| 03/27/2001 | US6207586 Oxide/nitride stacked gate dielectric and associated methods |
| 03/27/2001 | US6207585 Method of forming stacked insulating film and semiconductor device using the same |
| 03/27/2001 | US6207584 High dielectric constant material deposition to achieve high capacitance |
| 03/27/2001 | US6207583 Photoresist ashing process for organic and inorganic polymer dielectric materials |
| 03/27/2001 | US6207582 Provides both a chemical and a physical etching of the native oxide, without harming a gate oxide layer. |
| 03/27/2001 | US6207581 Method of fabricating node contact hole |
| 03/27/2001 | US6207580 Method of plasma etching the tungsten silicide layer in the gate conductor stack formation |
| 03/27/2001 | US6207579 Method of fabricating self-aligned node |
| 03/27/2001 | US6207578 Methods of forming patterned constructions, methods of patterning semiconductive substrates, and methods of forming field emission displays |
| 03/27/2001 | US6207577 Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer |
| 03/27/2001 | US6207576 Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide etch stop layer |
| 03/27/2001 | US6207575 Local interconnect etch characterization using AFM |
| 03/27/2001 | US6207574 Method for fabricating a DRAM cell storage node |
| 03/27/2001 | US6207573 Differential trench open process |
| 03/27/2001 | US6207572 Reverse linear chemical mechanical polisher with loadable housing |
| 03/27/2001 | US6207571 Self-aligned contact formation for semiconductor devices |
| 03/27/2001 | US6207570 Method for removing barrier material that lies between copper conductors in damascene interconnections, and a method for removing a thin layer of silicon nitride material that has been intentionally un-etched |
| 03/27/2001 | US6207569 Prevention of Cu dendrite formation and growth |
| 03/27/2001 | US6207568 Ionized metal plasma (IMP) method for forming (111) oriented aluminum containing conductor layer |
| 03/27/2001 | US6207567 Ti layer is formed with a collimator sputtering in the via opening or the contact opening of the substrate. through the control of flow of n2 and ar, a nitride mode tinx layer is formed on the ti layer by sputtering. |
| 03/27/2001 | US6207566 Method for forming a metal plug on a semiconductor wafer |
| 03/27/2001 | US6207565 Integrated process for ashing resist and treating silicon after masked spacer etch |
| 03/27/2001 | US6207564 Method of forming self-aligned isolated plugged contacts |
| 03/27/2001 | US6207563 Low-leakage CoSi2-processing by high temperature thermal processing |
| 03/27/2001 | US6207562 Method of forming titanium silicide |
| 03/27/2001 | US6207561 After metal deposition, the metal oxide is formed using an oxidation chemistry that includes co2 and h2. the co2/h2 gas ratio is controlled for selective oxidation. |
| 03/27/2001 | US6207560 Method for manufacturing thin-film resistor |
| 03/27/2001 | US6207559 Method of making a semiconductor device for attachment to a semiconductor substrate |
| 03/27/2001 | US6207558 For improved via fill in high aspect ratio sub-micron apertures at low temperature, particularly at the contact level on a substrate. |
| 03/27/2001 | US6207557 Method of forming multilayer titanium nitride film by multiple step chemical vapor deposition process and method of manufacturing semiconductor device using the same |
| 03/27/2001 | US6207556 Method of fabricating metal interconnect |
| 03/27/2001 | US6207555 Electron beam process during dual damascene processing |
| 03/27/2001 | US6207554 Gap filling process in integrated circuits using low dielectric constant materials |
| 03/27/2001 | US6207553 Method of forming multiple levels of patterned metallization |
| 03/27/2001 | US6207552 Forming and filling a recess in interconnect for encapsulation to minimize electromigration |
| 03/27/2001 | US6207551 Method and apparatus using formic acid vapor as reducing agent for copper wirebonding |
| 03/27/2001 | US6207550 Method for fabricating bump electrodes with a leveling step for uniform heights |
| 03/27/2001 | US6207549 Method of forming a ball bond using a bonding capillary |
| 03/27/2001 | US6207548 Method for fabricating a micromachined chip scale package |
| 03/27/2001 | US6207547 Bond pad design for integrated circuits |
| 03/27/2001 | US6207546 Prevent passivation from keyhole damage and resist extrusion by a crosslinking mechanism |
| 03/27/2001 | US6207545 Method for forming a T-shaped plug having increased contact area |
| 03/27/2001 | US6207544 Method of fabricating ultra thin nitride spacers and device incorporating same |
| 03/27/2001 | US6207543 Metallization technique for gate electrodes and local interconnects |
| 03/27/2001 | US6207542 Method for establishing ultra-thin gate insulator using oxidized nitride film |
| 03/27/2001 | US6207541 Method employing silicon nitride spacers for making an integrated circuit device |
| 03/27/2001 | US6207540 Method for manufacturing high performance MOSFET device with raised source and drain |
| 03/27/2001 | US6207539 Semiconductor device having field isolating film of which upper surface is flat and method thereof |
| 03/27/2001 | US6207538 Method for forming n and p wells in a semiconductor substrate using a single masking step |
| 03/27/2001 | US6207537 Method for formation of impurity region in semiconductor layer and apparatus for introducing impurity to semiconductor layer |
| 03/27/2001 | US6207536 Method for forming a thin film of a composite metal compound and apparatus for carrying out the method |
| 03/27/2001 | US6207535 Method of forming shallow trench isolation |
| 03/27/2001 | US6207534 Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing |
| 03/27/2001 | US6207533 Method for forming an integrated circuit |
| 03/27/2001 | US6207532 STI process for improving isolation for deep sub-micron application |
| 03/27/2001 | US6207531 Shallow trench isolation using UV/O3 passivation prior to trench fill |
| 03/27/2001 | US6207530 Dual gate FET and process |
| 03/27/2001 | US6207529 Semiconductor wafer,wafer alignment patterns and method of forming wafer alignment patterns |
| 03/27/2001 | US6207528 Method for fabricating capacitor of semiconductor device |
| 03/27/2001 | US6207527 Method of manufacturing semiconductor device |
| 03/27/2001 | US6207526 Method of fabricating an extended self-aligned crown-shaped rugged capacitor for high density DRAM cells |
| 03/27/2001 | US6207525 Method to fabricate electrodes for high-K dielectrics |
| 03/27/2001 | US6207524 Memory cell with a stacked capacitor |
| 03/27/2001 | US6207523 Methods of forming capacitors DRAM arrays, and monolithic integrated circuits |
| 03/27/2001 | US6207521 Thin-film resistor employed in a semiconductor wafer and its method formation |
| 03/27/2001 | US6207520 Rapid thermal anneal with a gaseous dopant species for formation of lightly doped regions |
| 03/27/2001 | US6207519 Method of making semiconductor device having double spacer |
| 03/27/2001 | US6207518 Method of manufacturing semiconductor device |
| 03/27/2001 | US6207517 Method of fabricating a semiconductor insulation layer and a semiconductor component containing the semiconductor insulation layer |
| 03/27/2001 | US6207516 Method of fabricating gate oxide layer with different thickness |
| 03/27/2001 | US6207515 Method of fabricating buried source to shrink chip size in memory array |
| 03/27/2001 | US6207514 Method for forming borderless gate structures and apparatus formed thereby |
| 03/27/2001 | US6207513 Spacer process to eliminate corner transistor device |
| 03/27/2001 | US6207512 Method and apparatus for improving latchup immunity in a dual-polysilicon gate process |
| 03/27/2001 | US6207511 Self-aligned trenched-channel lateral-current-flow transistor |
| 03/27/2001 | US6207510 Method for making an integrated circuit including high and low voltage transistors |
| 03/27/2001 | US6207509 Method of manufacturing a semiconductor device |
| 03/27/2001 | US6207508 Method for fabricating a radio frequency power MOSFET device having improved performance characteristics |
| 03/27/2001 | US6207507 Multi-level flash memory using triple well process and method of making |
| 03/27/2001 | US6207506 Nonvolatile memory and method for fabricating the same |
| 03/27/2001 | US6207505 Method for forming high density nonvolatile memories with high capacitive-coupling ratio |
| 03/27/2001 | US6207504 Method of fabricating flash erasable programmable read only memory |
| 03/27/2001 | US6207503 Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line |
| 03/27/2001 | US6207502 Method of using source/drain nitride for periphery field oxide and bit-line oxide |