| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 05/08/2001 | US6229186 Semiconductor memory device using inverter configuration |
| 05/08/2001 | US6229184 Semiconductor device with a modulated gate oxide thickness |
| 05/08/2001 | US6229182 Semiconductor device having protection against electrostatic discharge |
| 05/08/2001 | US6229179 Intelligent power integrated circuit |
| 05/08/2001 | US6229178 Vertical double diffused MOSFET and method for manufacturing same |
| 05/08/2001 | US6229177 Semiconductor with laterally non-uniform channel doping profile |
| 05/08/2001 | US6229176 Split gate flash with step poly to improve program speed |
| 05/08/2001 | US6229175 Nonvolatile memory |
| 05/08/2001 | US6229174 Contact structure for memory device |
| 05/08/2001 | US6229173 Hybrid 5F2 cell layout for buried surface strap aligned to vertical transistor |
| 05/08/2001 | US6229172 Semiconductor device and manufacturing method thereof |
| 05/08/2001 | US6229171 Storage element for semiconductor capacitor |
| 05/08/2001 | US6229170 Semiconductor memory cell |
| 05/08/2001 | US6229169 Memory cell configuration, method for fabricating it and methods for operating it |
| 05/08/2001 | US6229168 Ferroelectric capacitor and a method for manufacturing thereof |
| 05/08/2001 | US6229167 Semiconductor device and method of manufacturing the same |
| 05/08/2001 | US6229166 Ferroelectric random access memory device and fabrication method therefor |
| 05/08/2001 | US6229164 MOSFET with a thin gate insulating film |
| 05/08/2001 | US6229161 Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches |
| 05/08/2001 | US6229157 Method of forming a polysilicon diode and devices incorporating such diode |
| 05/08/2001 | US6229156 Inverted thin film transistor having a trapezoidal-shaped protective layer |
| 05/08/2001 | US6229155 Semiconductor and method of fabricating |
| 05/08/2001 | US6229149 Electron beam drawing apparatus and method of the same |
| 05/08/2001 | US6229148 Ion implantation with programmable energy, angle, and beam current |
| 05/08/2001 | US6229118 Wafer handling apparatus for transferring a wafer to and from a process chamber |
| 05/08/2001 | US6229116 Heat treatment apparatus |
| 05/08/2001 | US6229099 Multi-layer circuit board with particular pad spacing |
| 05/08/2001 | US6229088 Low profile electronic enclosure |
| 05/08/2001 | US6228823 Method for treating surface of substrate and surface treatment composition used for the same |
| 05/08/2001 | US6228782 Core field isolation for a NAND flash memory |
| 05/08/2001 | US6228781 Sequential in-situ heating and deposition of halogen-doped silicon oxide |
| 05/08/2001 | US6228780 Non-shrinkable passivation scheme for metal em improvement |
| 05/08/2001 | US6228779 Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology |
| 05/08/2001 | US6228778 Semiconductor device having improved insulation film and manufacturing method thereof |
| 05/08/2001 | US6228777 Integrated circuit with borderless contacts |
| 05/08/2001 | US6228775 Plasma etching method using low ionization potential gas |
| 05/08/2001 | US6228774 Flowing etchant source gas comprising methylene fluoride, perfluorobutylene and oxygen into plasma processing chamber, forming plasma from gas, etching through oxide layer of substrate with plasma, wherein etching stops on substrate |
| 05/08/2001 | US6228773 Synchronous multiplexed near zero overhead architecture for vacuum processes |
| 05/08/2001 | US6228772 Method of removing surface defects or other recesses during the formation of a semiconductor device |
| 05/08/2001 | US6228771 Chemical mechanical polishing process for low dishing of metal lines in semiconductor wafer fabrication |
| 05/08/2001 | US6228770 Method to form self-sealing air gaps between metal interconnects |
| 05/08/2001 | US6228769 Endpoint detection by chemical reaction and photoionization |
| 05/08/2001 | US6228768 Storage-annealing plated CU interconnects |
| 05/08/2001 | US6228767 Non-linear circuit elements on integrated circuits |
| 05/08/2001 | US6228766 Process for fabricating semiconductor device without separation between silicide layer and insulating layer |
| 05/08/2001 | US6228765 Structure and method for forming conductive members in an integrated circuit |
| 05/08/2001 | US6228764 Method of forming wiring in semiconductor device |
| 05/08/2001 | US6228763 Method of fabricating metal interconnect having inner air spacer |
| 05/08/2001 | US6228762 Methods for forming contact holes having sidewalls with smooth profiles |
| 05/08/2001 | US6228761 Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide |
| 05/08/2001 | US6228760 Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish |
| 05/08/2001 | US6228759 Method of forming an alloy precipitate to surround interconnect to minimize electromigration |
| 05/08/2001 | US6228758 Method of making dual damascene conductive interconnections and integrated circuit device comprising same |
| 05/08/2001 | US6228757 Process for forming metal interconnects with reduced or eliminated metal recess in vias |
| 05/08/2001 | US6228756 Method of manufacturing inter-metal dielectric layer |
| 05/08/2001 | US6228755 Semiconductor device, and manufacturing method therefor |
| 05/08/2001 | US6228754 Method for forming semiconductor seed layers by inert gas sputter etching |
| 05/08/2001 | US6228753 Method of fabricating a bonding pad structure for improving the bonding pad surface quality |
| 05/08/2001 | US6228752 Semiconductor device and method of manufacturing the same |
| 05/08/2001 | US6228751 Method of manufacturing a semiconductor device |
| 05/08/2001 | US6228750 Method of doping a semiconductor surface |
| 05/08/2001 | US6228749 Method of manufacturing semiconductor device |
| 05/08/2001 | US6228748 Use of a getter layer to improve metal to metal contact resistance at low radio frequency power |
| 05/08/2001 | US6228747 Organic sidewall spacers used with resist |
| 05/08/2001 | US6228746 Methodology for achieving dual field oxide thicknesses |
| 05/08/2001 | US6228745 Selective reduction of sidewall slope on isolation edge |
| 05/08/2001 | US6228743 Alignment method for semiconductor device |
| 05/08/2001 | US6228742 Method of fabricating shallow trench isolation structure |
| 05/08/2001 | US6228741 Method for trench isolation of semiconductor devices |
| 05/08/2001 | US6228740 Method of making an antireflective structure |
| 05/08/2001 | US6228739 Pre-treatment method performed on a semiconductor structure before forming hemi-spherical grains of capacitor storage node |
| 05/08/2001 | US6228738 Methods of forming capacitors structures and DRAM cells |
| 05/08/2001 | US6228737 Method of manufacturing semiconductor device |
| 05/08/2001 | US6228736 Modified method for forming cylinder-shaped capacitors for dynamic random access memory (DRAM) |
| 05/08/2001 | US6228735 Method of fabricating thin-film transistor |
| 05/08/2001 | US6228733 Non-selective epitaxial depostion technology |
| 05/08/2001 | US6228732 Tunnel nitride for improved polysilicon emitter |
| 05/08/2001 | US6228731 Re-etched spacer process for a self-aligned structure |
| 05/08/2001 | US6228730 Method of fabricating field effect transistor |
| 05/08/2001 | US6228729 MOS transistors having raised source and drain and interconnects |
| 05/08/2001 | US6228728 Method of fabricating semiconductor device |
| 05/08/2001 | US6228727 Method to form shallow trench isolations with rounded corners and reduced trench oxide recess |
| 05/08/2001 | US6228726 Method to suppress CMOS device latchup and improve interwell isolation |
| 05/08/2001 | US6228725 Semiconductor devices with pocket implant and counter doping |
| 05/08/2001 | US6228724 Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby |
| 05/08/2001 | US6228723 Method for forming split gate non-volatile memory cells without forming a conductive layer on a boundary region between a memory cell array and peripheral logic |
| 05/08/2001 | US6228722 Method for fabricating self-aligned metal silcide |
| 05/08/2001 | US6228721 Fabrication of metal oxide structures with different thicknesses on a semiconductor substrate |
| 05/08/2001 | US6228720 Method for making insulated-gate semiconductor element |
| 05/08/2001 | US6228719 MOS technology power device with low output resistance and low capacitance, and related manufacturing process |
| 05/08/2001 | US6228718 Method of fabricating a self-aligned split gate of a flash memory |
| 05/08/2001 | US6228717 Method of manufacturing semiconductor devices with alleviated electric field concentration at gate edge portions |
| 05/08/2001 | US6228716 Method of making damascene flash memory transistor |
| 05/08/2001 | US6228715 Semiconductor memory device and method of manufacturing thereof |
| 05/08/2001 | US6228714 Method for manufacturing nonvolatile memory device |
| 05/08/2001 | US6228713 Self-aligned floating gate for memory application using shallow trench isolation |
| 05/08/2001 | US6228712 Non-volatile semiconductor memory device and manufacturing method thereof |
| 05/08/2001 | US6228711 Method of fabricating dynamic random access memory |
| 05/08/2001 | US6228710 Methods of forming capacitors and DRAM arrays |
| 05/08/2001 | US6228709 Method of fabricating hemispherical grain electrode |