Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2001
05/15/2001US6232637 Semiconductor fabrication having multi-level transistors and high density interconnect therebetween
05/15/2001US6232636 Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region
05/15/2001US6232635 Method to fabricate a high coupling flash cell with less silicide seam problem
05/15/2001US6232633 NVRAM cell using sharp tip for tunnel erase
05/15/2001US6232632 Double density non-volatile memory cells
05/15/2001US6232631 Floating gate memory cell structure with programming mechanism outside the read path
05/15/2001US6232629 Ferroelectric capacitor and a method for manufacturing thereof
05/15/2001US6232628 Semiconductor device having stacked capacitor structure
05/15/2001US6232623 Semiconductor device on a sapphire substrate
05/15/2001US6232622 Semiconductor device with high electric field effect mobility
05/15/2001US6232621 Semiconductor device and method of fabricating the same
05/15/2001US6232619 Dosage micro uniformity measurement in ion implantation
05/15/2001US6232615 Lithographic projection apparatus with improved substrate holder
05/15/2001US6232612 Variable shaped electron beam exposure system and method of writing a pattern by a variable shaped electron beam
05/15/2001US6232580 Apparatus for uniform gas and radiant heat dispersion for solid state fabrication processes
05/15/2001US6232578 Thermophoretic vacuum wand
05/15/2001US6232563 Bump electrode and method for fabricating the same
05/15/2001US6232561 Process for producing wire connections on an electronic component assembly carrier made by the process
05/15/2001US6232558 Electronic component mounting base board having heat slug with slits and projections
05/15/2001US6232248 Single-substrate-heat-processing method for performing reformation and crystallization
05/15/2001US6232247 Substrate coating apparatus and semiconductor processing method of improving uniformity of liquid deposition
05/15/2001US6232246 Method of fabricating semiconductor device
05/15/2001US6232245 Method of forming interlayer film
05/15/2001US6232244 Methodology for achieving dual gate oxide thicknesses
05/15/2001US6232242 Method of forming a crystalline insulation layer on a silicon substrate
05/15/2001US6232241 Pre-oxidation cleaning method for reducing leakage current of ultra-thin gate oxide
05/15/2001US6232240 Method for fabricating a capacitor
05/15/2001US6232239 Method for cleaning contact holes in a semiconductor device
05/15/2001US6232238 Method for preventing corrosion of bonding pad on a surface of a semiconductor wafer
05/15/2001US6232237 Method for fabricating semiconductor device
05/15/2001US6232235 Method of forming a semiconductor device
05/15/2001US6232233 Methods for performing planarization and recess etches and apparatus therefor
05/15/2001US6232232 High selectivity BPSG to TEOS etchant
05/15/2001US6232231 Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
05/15/2001US6232230 Semiconductor interconnect interface processing by high temperature deposition
05/15/2001US6232229 Microelectronic device fabricating method, integrated circuit, and intermediate construction
05/15/2001US6232228 Formation of a conductive plug and the minimizing of the step-height of an interlayer dielectric layer.
05/15/2001US6232227 Method for making semiconductor device
05/15/2001US6232226 Method of fabricating barrier layer in integrated circuit
05/15/2001US6232225 Method of fabricating contact window of semiconductor device
05/15/2001US6232224 Method of manufacturing semiconductor device having reliable contact structure
05/15/2001US6232222 Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure
05/15/2001US6232221 Borderless vias
05/15/2001US6232220 Method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped zones
05/15/2001US6232219 Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures
05/15/2001US6232218 Etch stop for use in etching of silicon oxide
05/15/2001US6232217 Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening
05/15/2001US6232216 Thin film forming method
05/15/2001US6232215 Method for forming increased density for interconnection metallization
05/15/2001US6232214 Method for fabricating inter-metal dielectric layer
05/15/2001US6232212 Flip chip bump bonding
05/15/2001US6232211 Two-step projecting bump for semiconductor chip and method for forming the same
05/15/2001US6232209 Semiconductor device and manufacturing method thereof
05/15/2001US6232208 Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile
05/15/2001US6232207 Doping process for producing homojunctions in semiconductor substrates
05/15/2001US6232206 Method for forming electrostatic discharge (ESD) protection transistors
05/15/2001US6232205 Method for producing a semiconductor device
05/15/2001US6232204 Semiconductor manufacturing system with getter safety device
05/15/2001US6232203 Process for making improved shallow trench isolation by employing nitride spacers in the formation of the trenches
05/15/2001US6232202 Method for manufacturing shallow trench isolation structure including a dual trench
05/15/2001US6232201 Semiconductor substrate processing method
05/15/2001US6232200 Method of reconstructing alignment mark during STI process
05/15/2001US6232199 Method for forming a multi-cylinder capacitor
05/15/2001US6232198 Method for fabricating electrode
05/15/2001US6232197 Metal-insulator-metal capacitor
05/15/2001US6232196 Method of depositing silicon with high step coverage
05/15/2001US6232195 Structure of semiconductor device
05/15/2001US6232194 Silicon nitride capped poly resistor with SAC process
05/15/2001US6232193 Method of forming isolated integrated injection logic gate
05/15/2001US6232192 Method of manufacturing semiconductor device having sidewall portions removed
05/15/2001US6232191 Method for forming a spacer for semiconductor manufacture
05/15/2001US6232190 Method of forming junction diodes
05/15/2001US6232189 Manufacturing method of semiconductor device
05/15/2001US6232188 CMP-free disposable gate process
05/15/2001US6232187 Semiconductor device and manufacturing method thereof
05/15/2001US6232185 Method of making a floating gate memory cell
05/15/2001US6232184 Method of manufacturing floating gate of stacked-gate nonvolatile memory unit
05/15/2001US6232183 Method for fabricating a flash memory
05/15/2001US6232182 Non-volatile semiconductor memory device including memory transistor with a composite gate structure and method of manufacturing the same
05/15/2001US6232181 Method of forming a flash memory
05/15/2001US6232180 Split gate flash memory cell
05/15/2001US6232179 Semiconductor device and method of manufacturing the same
05/15/2001US6232178 Method for manufacturing capacitive element
05/15/2001US6232177 Method for increasing surface area of a bottom electrode for a DRAM
05/15/2001US6232176 Integrated circuitry, DRAM cells, capacitors, and methods of forming integrated circuitry, DRAM cells and capacitors
05/15/2001US6232175 Method of manufacturing double-recess crown-shaped DRAM capacitor
05/15/2001US6232174 Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film
05/15/2001US6232173 Process for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one substrate and process for forming a new NVRAM cell structure
05/15/2001US6232171 Technique of bottle-shaped deep trench formation
05/15/2001US6232170 Method of fabricating trench for SOI merged logic DRAM
05/15/2001US6232169 Method for producing a capacitor
05/15/2001US6232168 Memory circuitry and method of forming memory circuitry
05/15/2001US6232167 Method of producing a ferroelectric thin film coated substrate
05/15/2001US6232166 CMOS processing employing zero degree halo implant for P-channel transistor
05/15/2001US6232165 Buried guard rings and method for forming the same
05/15/2001US6232164 Process of making CMOS device structure having an anti-SCE block implant
05/15/2001US6232162 Method of complementary metal-oxide semiconductor
05/15/2001US6232161 Method for forming a dummy active pattern
05/15/2001US6232160 Method of delta-channel in deep sub-micron process
05/15/2001US6232159 Method for fabricating compound semiconductor device