Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2001
05/22/2001US6236449 Illumination optical apparatus and exposure apparatus
05/22/2001US6236447 Exposure method and apparatus, and semiconductor device manufactured using the method
05/22/2001US6236327 Wafer-fetching sensing device for wafer storage apparatus
05/22/2001US6236258 Wordline driver circuit using ring-shaped devices
05/22/2001US6236256 Voltage level converters
05/22/2001US6236239 Output buffer circuit achieving stable operation and cost reduction
05/22/2001US6236117 Semiconductor memory device including shunt interconnection
05/22/2001US6236113 Iridium composite barrier structure and method for same
05/22/2001US6236112 Semiconductor device, connecting substrate therefor, and process of manufacturing connecting substrate
05/22/2001US6236106 Wiring structure with divided wiring conductors to achieve planarity in an overlying SOG layer
05/22/2001US6236105 Semiconductor device with improved planarity achieved through interlayer films with varying ozone concentrations
05/22/2001US6236104 Silicon on insulator structure from low defect density single crystal silicon
05/22/2001US6236103 Integrated high-performance decoupling capacitor and heat sink
05/22/2001US6236101 Metallization outside protective overcoat for improved capacitors and inductors
05/22/2001US6236100 Semiconductor with high-voltage components and low-voltage components on a shared die
05/22/2001US6236094 Low resistance gate electrodes
05/22/2001US6236093 Semiconductor device including gate electrode having polymetal structure and method of manufacturing of the same
05/22/2001US6236091 Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide
05/22/2001US6236090 Semiconductor device and method for reducing contact resistance between an electrode and a semiconductor substrate
05/22/2001US6236089 CMOSFET and method for fabricating the same
05/22/2001US6236084 Semiconductor integrated circuit device having double diffusion insulated gate field effect transistor
05/22/2001US6236083 Power device
05/22/2001US6236082 Floating gate semiconductor device with reduced erase voltage
05/22/2001US6236081 AND-type non-volatile semiconductor memory device and method of manufacturing thereof
05/22/2001US6236080 Method of manufacturing a capacitor for high density DRAMs
05/22/2001US6236079 Dynamic semiconductor memory device having a trench capacitor
05/22/2001US6236078 Semiconductor memory device
05/22/2001US6236077 Trench electrode with intermediate conductive barrier layer
05/22/2001US6236076 Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material
05/22/2001US6236074 Solid state image sensor device and method of fabricating the same
05/22/2001US6236072 Method and system for emitter partitioning for SiGe RF power transistors
05/22/2001US6236070 Mes/mis fet
05/22/2001US6236064 Electro-optical device
05/22/2001US6236063 Semiconductor device
05/22/2001US6236062 Liquid crystal display and thin film transistor with capacitive electrode structure
05/22/2001US6236061 Semiconductor crystallization on composite polymer substrates
05/22/2001US6236059 Memory cell incorporating a chalcogenide element and method of making same
05/22/2001US6236057 Method of inspecting pattern and apparatus thereof with a differential brightness image detection
05/22/2001US6236052 Quadrupole device for projection lithography by means of charged particles
05/22/2001US6236033 Enhanced optical transmission apparatus utilizing metal films having apertures and periodic surface topography
05/22/2001US6236015 Method for predicting and avoiding a bad bond when utilizing fiber push connect laser bonding
05/22/2001US6235996 Interconnection structure and process module assembly and rework
05/22/2001US6235862 At least the surfaces of the sheet that contact the semiconductor chip and attachment site are a semi-cured product of a curable silicone composition.
05/22/2001US6235836 Photoresists prepared from the protected copolymers can enhance the resolution of fine circuit by virtue of low weight loss upon the thermal treatment after exposure.
05/22/2001US6235718 Compounds for control of appetite, blood pressure, cardiovascular response, libido, and circadian rhythm
05/22/2001US6235693 Cleaning semiconductors after etching
05/22/2001US6235656 Dual degas/cool loadlock cluster tool
05/22/2001US6235655 Semiconductor manufacturing system and semiconductor manufacturing method
05/22/2001US6235654 Process for forming PECVD nitride with a very low deposition rate
05/22/2001US6235653 Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer
05/22/2001US6235652 High rate silicon dioxide deposition at low pressures
05/22/2001US6235651 Process for improving the thickness uniformity of a thin layer in semiconductor wafer fabrication
05/22/2001US6235650 Passivation; protective coating
05/22/2001US6235649 Method of forming high dielectric constant thin film and method of manufacturing semiconductor device
05/22/2001US6235648 Semiconductor device including insulation film and fabrication method thereof
05/22/2001US6235647 Deposition process for forming void-free dielectric layer
05/22/2001US6235646 RF powered plasma enhanced chemical vapor deposition reactor and methods of effecting plasma enhanced chemical vapor deposition
05/22/2001US6235645 Process for cleaning silicon semiconductor substrates
05/22/2001US6235644 Method of improving etch back process
05/22/2001US6235643 Method for etching a trench having rounded top and bottom corners in a silicon substrate
05/22/2001US6235641 Method and system to control the concentration of dissolved gas in a liquid
05/22/2001US6235640 Techniques for forming contact holes through to a silicon layer of a substrate
05/22/2001US6235639 Method of making straight wall containers and the resultant containers
05/22/2001US6235636 Resist removal by polishing
05/22/2001US6235635 Linear CMP tool design using in-situ slurry distribution and concurrent pad conditioning
05/22/2001US6235634 Modular substrate processing system
05/22/2001US6235633 Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process
05/22/2001US6235632 Tungsten plug formation
05/22/2001US6235631 Vapor deposition; reacting dimethylaluminum hydride with tetrakis/dimethylamido/titanium
05/22/2001US6235630 Silicide pattern structures and methods of fabricating the same
05/22/2001US6235629 Process for producing a semiconductor device
05/22/2001US6235628 Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer
05/22/2001US6235627 Semiconductor device and method for manufacturing the same
05/22/2001US6235626 Method of forming a gate electrode using an insulating film with an opening pattern
05/22/2001US6235625 Method of fabricating copper damascene
05/22/2001US6235624 Paste connection plug, burying method, and semiconductor device manufacturing method
05/22/2001US6235623 Methods of forming integrated circuit contact holes using blocking layer patterns
05/22/2001US6235622 Method and apparatus for isolating a conductive region from a substrate during manufacture of an integrated circuit and connected to the substrate after manufacture
05/22/2001US6235621 Method for forming a semiconductor device
05/22/2001US6235620 Process for manufacturing semiconductor integrated circuit device
05/22/2001US6235619 Manufacturing method for reduced semiconductor memory device contact holes with minimal damage to device separation characteristics
05/22/2001US6235618 Method for forming nanometer-sized silicon quantum dots
05/22/2001US6235617 Semiconductor device and its manufacturing method
05/22/2001US6235616 Method of ion implantation into silicon carbide semiconductors
05/22/2001US6235614 Methods of crystallizing amorphous silicon layer and fabricating thin film transistor using the same
05/22/2001US6235613 Method of producing HSG using an amorphous silicon disordered layer as a substrate
05/22/2001US6235612 Edge bond pads on integrated circuits
05/22/2001US6235610 Process for selectively implanting dopants into the bottom of a deep trench
05/22/2001US6235609 Method for forming isolation areas with improved isolation oxide
05/22/2001US6235608 STI process by method of in-situ multilayer dielectric deposition
05/22/2001US6235607 Method for establishing component isolation regions in SOI semiconductor device
05/22/2001US6235606 Method of fabricating shallow trench isolation
05/22/2001US6235605 Selective silicon formation for semiconductor devices
05/22/2001US6235604 Manufacturing process for a capacitor
05/22/2001US6235603 Method for forming a semiconductor device using an etch stop layer
05/22/2001US6235602 Method for fabricating semiconductor device
05/22/2001US6235601 Method of manufacturing a self-aligned vertical bipolar transistor
05/22/2001US6235600 Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition
05/22/2001US6235599 Fabrication of a shallow doped junction having low sheet resistance using multiple implantations
05/22/2001US6235598 Method of using thick first spacers to improve salicide resistance on polysilicon gates