Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2001
05/25/2001WO2001036990A2 Wafer level interposer
05/25/2001WO2001036986A1 Probe card
05/25/2001WO2001036917A1 Integrated circuit device and correction method for integrated circuit device
05/25/2001WO2001036901A2 Systems and methods for quantifying nonlinearities in interferometry systems
05/25/2001WO2001036719A1 Silicon single crystal wafer and production method thereof and soi wafer
05/25/2001WO2001036718A1 Silicon wafer and production method thereof and evaluation method for silicon wafer
05/25/2001WO2001036703A1 System and method for depositing inorganic/organic dielectric films
05/25/2001WO2001036702A1 Method of vaporizing liquid sources and apparatus therefor
05/25/2001WO2001036578A1 Non-corrosive cleaning composition for removing plasma etching residues
05/25/2001WO2001036555A1 Composition and method for planarizing surfaces
05/25/2001WO2001036554A1 Composition and method for planarizing surfaces
05/25/2001WO2001036349A1 Method for attaching a body, which is comprised of a metal matrix composite (mmc) material, to a ceramic body
05/25/2001WO2001036181A1 Method of dry-etching resin film and device therefor
05/25/2001WO2001036148A1 Solder alloy, electronic member having solder ball and solder bump
05/25/2001WO2001035718A2 System and method for product yield prediction
05/25/2001WO2001022475A3 Method for dicing mesa-diodes
05/25/2001WO2001003183A3 Method for applying connecting materials for connecting a microchip and a substrate and utilization of a printing head working according to the ink printing principle
05/25/2001WO2000051782B1 Apparatus and method for chemical-mechanical polishing (cmp) using a head having direct pneumatic wafer polishing pressure system
05/25/2001CA2360441A1 Semiconductor laser device
05/24/2001US20010001839 Apparatus, method and medium for enhancing the throughput of a wafer processing facility using a multi-slot cool down chamber and a priority transfer scheme
05/24/2001US20010001785 A cleaning composition for removing plasma etch residues formed on a substrate which comprises water, atleast one hydroxylammonium inorganic or organic compound, a basic compound and an organic carboxyllic acid
05/24/2001US20010001746 High efficiency photoresist coating
05/24/2001US20010001745 By localized irradiation of teh film with pulses of laser radiation, locally to melt the film through its entire thickness, the melt then solidifies laterally from a seed area; pixel controllers in liquid crystal displays
05/24/2001US20010001744 Semiconductor device and method of manufacturing the same
05/24/2001US20010001743 Inductively coupled plasma etching in a reactor by flowing oxygen, helium and argon gas into the reactor, striking a plasma, then adding sulfur fluoride (SF6) gas in given flow ratios
05/24/2001US20010001742 Method of fabricating a dual -damascene structure in an integrated cirtcuit with multilevel-interconnect strcture
05/24/2001US20010001741 Process for the production of semiconductor device
05/24/2001US20010001740 Semiconductor encapsulated in a hollow package, made by housing a chip in a plurality of cavities of a plate-like substrate, bonding a plate-like cap to teh substrate, and separating the bonded members along space between cavities
05/24/2001US20010001739 In which an insulating film with a low dielectric constant is formed by an ordinary resist application process
05/24/2001US20010001737 Apparatus for etching glass substrate
05/24/2001US20010001736 Cleaning semiconductor wafer by spraying a first heated solvent such as N-methylpyrrolidine, discontinuing spraying, then spraying a second solvent at around room temperature, discontinuing spraying; high throughput cleaning
05/24/2001US20010001734 Depositing indium phosphide on diffraction grating by metal organic chemical vapor deposition (MOCVD), heating substrate and depositing second layer at higher growth rate; diffraction grating with high accuracy; semiconductor laser
05/24/2001US20010001733 Improved method for selectively etching a semiconductor device
05/24/2001US20010001732 Masking a silicon oxide(SiO2) layer on a polysilicon (Si) layer, the SiO2 and Si layer are respectively etched such as with tetrafluoromethane and hydrogen bromide and oxygen, etching fluorocarbon residue such as with chlorine gas
05/24/2001US20010001731 Forming a layer over uneven surface having a valley between projections, the layer having projections and a gap over the valley, etching the layer which forms protective material in the gap while removing outermost layer
05/24/2001US20010001730 Enhancing semiconductor structure surface area using hsg and etching
05/24/2001US20010001729 Etching arsenic-doped polysilicon layer on a patterned borophosphosilicate glass layer on a substrte mounted in a plasma etch reactor on an electrostatic chuck using a given ratio of nitrogen trifluoride and trifluoromethane
05/24/2001US20010001728 Selective nitride etching with silicate ion pre-loading
05/24/2001US20010001727 By forming a protective film on the surface by High-Density Plasma Chemical Vapor Deposition; better filling of gaps between metal lines
05/24/2001US20010001726 Methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry
05/24/2001US20010001725 Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer
05/24/2001US20010001724 First strip of metallic conductive material of given stress, overlying a narrower strip of a second conductive material of lower stress; destructive interference between layers lowers edge stress in underlying structures; integrated circuits
05/24/2001US20010001723 Nitrogenated trench liner for improved shallow trench isolation
05/24/2001US20010001722 Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
05/24/2001US20010001721 Masking polysilicon (PS) layer of transistors of the read only memory (ROM) cell, doping the ROM cells in the active areas of the exposed transistors, demasking the PS layer and implanting a second dopant in previously covered layer
05/24/2001US20010001720 Mini flash process and circuit
05/24/2001US20010001719 Method of fabricating trench for soi merged logic dram
05/24/2001US20010001718 Semiconductor integrated circuit device and method of manufacture thereof
05/24/2001US20010001717 Oxidation on surface of film of refractory metal constituting gate electrode is suppressed by forming cap insulation film of the gate electrode at a temperature of 500 degrees
05/24/2001US20010001716 Forming an amorphous silicon thin-film on a glass substrate, crystallizing the amorphous silicon of the thin-film transistor according to a scanning method using a linear light beam; nondeforming of glass substrate
05/24/2001US20010001715 Forming an amorphous silicon thin-film on a glass substrate, crystallizing the amorphous silicon of the thin-film transistor according to a scanning method using a linear light beam
05/24/2001US20010001714 Forming electronic circuit on wafer in region defined by scribe line, attaching circuit substrate carrying predetermined conductor pattern on wafer, interconnecting by wire bonding, forming spherical electrode, dicing
05/24/2001US20010001707 Treatment on silicon oxynitride
05/24/2001US20010001703 Method for the formation of resist patterns
05/24/2001US20010001694 Semiconductive material stencil mask, methods of manufacturing stencil masks from semiconductive material, and methods for maintaining dimensions of openings in semiconductive materials stencil masks
05/24/2001US20010001678 Method of forming an intermetal dielectric layer
05/24/2001US20010001589 Thin film structure that may be used with an adhesion layer
05/24/2001US20010001583 Diffractive optical element and optical sysetm incorporating the same
05/24/2001US20010001577 Exposure apparatus and device manufacturing method including measuring position and/or displacement of each of a base and a stage with respect to a support
05/24/2001US20010001538 Wafer probe station having environment control enclosure
05/24/2001US20010001504 Semiconductor device
05/24/2001US20010001503 Contact level via and method of selective formation of a barrier layer for a contact level via
05/24/2001US20010001502 Fill pattern in kerf areas to prevent localized non-uniformities of insulating layers at die corners on semiconductor substrates
05/24/2001US20010001501 Methods of forming integrated circuit capacitors having doped HSG electrodes and capacitors formed thereby
05/24/2001US20010001500 Semiconductor device and method for producing same
05/24/2001US20010001498 Field effect transistors, integrated circuitry, methods of forming field effect transistor gates, and methods of forming integrated circuitry
05/24/2001US20010001497 Semiconductor device and method for manufacturing the same
05/24/2001US20010001496 Semiconductor devices
05/24/2001US20010001495 Method for reducing contact resistance
05/24/2001US20010001494 Power trench mos-gated device and process for forming same
05/24/2001US20010001493 Regulating resistor network, semiconductor device including the resistor network, and method for fabricating the device
05/24/2001US20010001492 Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips
05/24/2001US20010001491 Semiconductor memory device having memory cells each having a conductive body of booster plate and a method for manufacturing the same
05/24/2001US20010001490 Device with differential field isolation thicknesses and related methods
05/24/2001US20010001489 Methods of forming capacitors, and methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions
05/24/2001US20010001488 Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer
05/24/2001US20010001486 Dual gate fet and process
05/24/2001US20010001484 Semiconductor configuration with ohmic contact-connection and method for contact-connecting a semiconductor configuration
05/24/2001US20010001483 Dynamic threshold voltage devices with low gate to substrate resistance
05/24/2001US20010001482 Process for fabricating thin-film device and thin-film device
05/24/2001US20010001469 Method and apparatus for mounting component
05/24/2001US20010001463 Heating device, method for evaluating heating device and pattern forming method
05/24/2001US20010001437 Capable of preventing a work piece from being excessively heated and capable of stably machining the work piece; holding unit comprises holder for holding a work piece, pressing member, heat insulating member
05/24/2001US20010001428 Circuit board and semiconductor device, and method of manufacturing the same
05/24/2001US20010001427 Electrical interconnect structure and method of forming electrical interconnects having electromigration-inhibiting segments
05/24/2001US20010001413 Method and apparatus for increasing wafer throughput between cleanings in semiconductor processing reactors
05/24/2001US20010001407 Removes significant proportion of mutagens and carcinogens; retains smoke flavor, nicotine content, and draw character-istics; inexpensive, safe
05/24/2001US20010001406 Embossing a channel or opening into the green tape of the desired size under heat and pressure, screen printing an ink of conductive material to fill embossed channel or openings, firing the green tape
05/24/2001US20010001401 Process for producing a metal article
05/24/2001US20010001393 Displacing the substrae relative to a rinsing liquid after the substrate is rinsed in a rinsing bath in which rinsing liquid is contained, thus preventing water droplets from remaining between the substrate and holder
05/24/2001US20010001392 Substrate treating method and apparatus
05/24/2001US20010001391 Plurality of electron-hole pairs are created using photon energy near a surface of the wafer and wafer is heated to desorb any of the plurality contaminant ions and molecules adsorbed on the surface of the wafer
05/24/2001US20010001386 Control apparatus and control method
05/23/2001EP1102525A1 Printed wiring board and method for producing the same
05/23/2001EP1102467A1 Solid-state imaging device, method for driving the same, and image input device
05/23/2001EP1102401A1 Bus driver circuit and method for operating the same
05/23/2001EP1102370A1 Semiconductor module and method of mounting semiconductor laser element on the same
05/23/2001EP1102368A2 Narrow-band excimer laser apparatus
05/23/2001EP1102335A2 Thin film transistors
05/23/2001EP1102329A2 Dielectric element