| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 05/29/2001 | US6239042 Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices |
| 05/29/2001 | US6239041 Method for fabricating semiconductor integrated circuit device |
| 05/29/2001 | US6239040 Method of coating amorphous silicon film |
| 05/29/2001 | US6239039 Semiconductor wafers processing method and semiconductor wafers produced by the same |
| 05/29/2001 | US6239038 Method for chemical processing semiconductor wafers |
| 05/29/2001 | US6239037 Autoaligned etching process for realizing word lines and improving the reliability of semiconductor integrated memory devices |
| 05/29/2001 | US6239036 Apparatus and method for plasma etching |
| 05/29/2001 | US6239035 Semiconductor wafer fabrication |
| 05/29/2001 | US6239034 Method of manufacturing inter-metal dielectric layers for semiconductor devices |
| 05/29/2001 | US6239033 Making a device using nitride iii-v compound semiconductors on one major surface of a single-crystal substrate; thinning said single-crystal substrate by processing the other major surface |
| 05/29/2001 | US6239032 Polishing method |
| 05/29/2001 | US6239030 Method of fabricating a trench isolation structure for a semiconductor device |
| 05/29/2001 | US6239029 Sacrificial germanium layer for formation of a contact |
| 05/29/2001 | US6239028 Methods for forming iridium-containing films on substrates |
| 05/29/2001 | US6239027 Method using a photoresist residue |
| 05/29/2001 | US6239026 Nitride etch stop for poisoned unlanded vias |
| 05/29/2001 | US6239025 High aspect ratio contact structure for use in integrated circuits |
| 05/29/2001 | US6239024 Method of filling gap with dielectrics |
| 05/29/2001 | US6239023 Method to reduce the damages of copper lines |
| 05/29/2001 | US6239022 Method of fabricating a contact in a semiconductor device |
| 05/29/2001 | US6239021 Dual barrier and conductor deposition in a dual damascene process for semiconductors |
| 05/29/2001 | US6239020 Method for forming interlayer dielectric layer |
| 05/29/2001 | US6239018 Method for forming dielectric layers |
| 05/29/2001 | US6239017 Dual damascene CMP process with BPSG reflowed contact hole |
| 05/29/2001 | US6239016 Multilevel interconnection in a semiconductor device and method for forming the same |
| 05/29/2001 | US6239015 Semiconductor device having polysilicon interconnections and method of making same |
| 05/29/2001 | US6239014 Use of a silicon oxide component, used as part of the capping, composite shape, employed to reduce the coupling capacitance generated by the proximity of the tungsten bit line structure, to adjacent conductive structures. |
| 05/29/2001 | US6239013 Method for transferring particles from an adhesive sheet to a substrate |
| 05/29/2001 | US6239011 Using a silicon nitride gate sidewall and a silicon nitride gate cap; bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. |
| 05/29/2001 | US6239010 Method for manually manufacturing capacitor |
| 05/29/2001 | US6239009 Flash memory device and method for manufacturing the same |
| 05/29/2001 | US6239008 Method of making a density multiplier for semiconductor device manufacturing |
| 05/29/2001 | US6239007 Method of forming T-shaped gate |
| 05/29/2001 | US6239006 Native oxide removal with fluorinated chemistry before cobalt silicide formation |
| 05/29/2001 | US6239005 A platinum layer is epitaxially grown in a crystal orientation of by sputtering; after annealing at 600-900 degrees c., a buffer layer made of gallium nitride is epitaxially grown on the platinum layer |
| 05/29/2001 | US6239004 Method of forming oxide film on an SOI layer and method of fabricating a bonded wafer |
| 05/29/2001 | US6239003 Method of simultaneous fabrication of isolation and gate regions in a semiconductor device |
| 05/29/2001 | US6239002 Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer |
| 05/29/2001 | US6239001 Method for making a semiconductor device |
| 05/29/2001 | US6239000 Method of forming isolation structure for isolating high voltage devices |
| 05/29/2001 | US6238999 Isolation region forming methods |
| 05/29/2001 | US6238998 Shallow trench isolation on a silicon substrate using nitrogen implant into the side wall |
| 05/29/2001 | US6238997 Method of fabricating shallow trench isolation |
| 05/29/2001 | US6238996 Method of forming a shallow trench isolation structure |
| 05/29/2001 | US6238995 Method for forming layer of hemispherical grains and for fabricating a capacitor of a semiconductor device |
| 05/29/2001 | US6238994 Method of creating a rough electrode (high surface area) from Ti and TiN and resulting article |
| 05/29/2001 | US6238993 Polysilicon load for 4T SRAM operation at cold temperatures |
| 05/29/2001 | US6238991 Fabrication process of semiconductor device having an epitaxial substrate |
| 05/29/2001 | US6238990 Method for heat treatment of SOI wafer and SOI wafer heat-treated by the method |
| 05/29/2001 | US6238989 Process of forming self-aligned silicide on source/drain region |
| 05/29/2001 | US6238988 Method of forming a MOS transistor |
| 05/29/2001 | US6238987 Method to reduce parasitic capacitance |
| 05/29/2001 | US6238986 Formation of junctions by diffusion from a doped film at silicidation |
| 05/29/2001 | US6238985 Semiconductor device and method for fabricating the same |
| 05/29/2001 | US6238984 Integrating high voltage and low voltage device with silicide block mask |
| 05/29/2001 | US6238983 Alignment dip back oxide and code implant through poly to approach the depletion mode device character |
| 05/29/2001 | US6238982 Multiple threshold voltage semiconductor device fabrication technology |
| 05/29/2001 | US6238981 Process for forming MOS-gated devices having self-aligned trenches |
| 05/29/2001 | US6238980 Method for manufacturing silicon carbide MOS semiconductor device including utilizing difference in mask edges in implanting |
| 05/29/2001 | US6238979 Process for fabricating EEPROM memory cell array embedded on core CMOS |
| 05/29/2001 | US6238978 Use of etch to blunt gate corners |
| 05/29/2001 | US6238977 Method for fabricating a nonvolatile memory including implanting the source region, forming the first spacers, implanting the drain regions, forming the second spacers, and forming a source line on the source and second spacers |
| 05/29/2001 | US6238976 Method for forming high density flash memory |
| 05/29/2001 | US6238975 Method for improving electrostatic discharge (ESD) robustness |
| 05/29/2001 | US6238974 Method of forming DRAM capacitors with a native oxide etch-stop |
| 05/29/2001 | US6238973 Method for fabricating capacitors with hemispherical grains |
| 05/29/2001 | US6238972 Method for increasing capacitance |
| 05/29/2001 | US6238971 Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures |
| 05/29/2001 | US6238970 Method for fabricating a DRAM cell capacitor including etching upper conductive layer with etching byproduct forming an etch barrier on the conductive pattern |
| 05/29/2001 | US6238969 Method of forming a capacitor |
| 05/29/2001 | US6238968 Methods of forming integrated circuit capacitors having protected layers of HSG silicon therein |
| 05/29/2001 | US6238967 Method of forming embedded DRAM structure |
| 05/29/2001 | US6238966 Semiconductor memory device and method for fabricating the same |
| 05/29/2001 | US6238965 Method for forming a titanium dioxide layer |
| 05/29/2001 | US6238964 Method of fabricating a capacitor in a semiconductor device |
| 05/29/2001 | US6238963 Damascene process for forming ferroelectric capacitors |
| 05/29/2001 | US6238962 Method of fabricating static random access memory cell with vertically arranged drive transistors |
| 05/29/2001 | US6238961 Semiconductor integrated circuit device and process for manufacturing the same |
| 05/29/2001 | US6238960 Fast MOSFET with low-doped source/drain |
| 05/29/2001 | US6238959 Method of fabricating LDMOS transistor |
| 05/29/2001 | US6238958 Method for forming a transistor with reduced source/drain series resistance |
| 05/29/2001 | US6238957 Forming sacrificial fluorine containing layer on polycrystalline thin film layer by chemical vapor deposition using wf6 and sih4; forming si--f bonds within the thin film layer; removing the sacrificial layer |
| 05/29/2001 | US6238956 Method for manufacturing thin film transistor by using a self-align technology |
| 05/29/2001 | US6238952 Low-pin-count chip package and manufacturing method thereof |
| 05/29/2001 | US6238951 Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate |
| 05/29/2001 | US6238949 Method and apparatus for forming a plastic chip on chip package module |
| 05/29/2001 | US6238948 Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material |
| 05/29/2001 | US6238947 That permits etching of gan based compound semiconductor layers that allows the formation near a light-emitting layer of a current blocking layer for defining a current injection region |
| 05/29/2001 | US6238946 Process for fabricating single crystal resonant devices that are compatible with integrated circuit processing |
| 05/29/2001 | US6238942 Method of wire-bonding a repair die in a multi-chip module using a repair solution generated during testing of the module |
| 05/29/2001 | US6238940 Intra-tool defect offset system |
| 05/29/2001 | US6238939 Method of quality control in semiconductor device fabrication |
| 05/29/2001 | US6238938 Methods of making microelectronic connections with liquid conductive elements |
| 05/29/2001 | US6238937 Determining endpoint in etching processes using principal components analysis of optical emission spectra with thresholding |
| 05/29/2001 | US6238936 Method of using critical dimension mapping to qualify a new integrated circuit fabrication etch process |
| 05/29/2001 | US6238935 Silicon-on-insulator wafer having conductive layer for detection with electrical sensors |
| 05/29/2001 | US6238934 Method for fabricating ferroelectric capacitor with improved interface surface characteristic |
| 05/29/2001 | US6238933 Polarization method for minimizing the effects of hydrogen damage on ferroelectric thin film capacitors |
| 05/29/2001 | US6238932 Method for fabricating reliable multilayer bottom electrode for ferroelectric capacitors |
| 05/29/2001 | US6238848 Developing method and developing apparatus |