| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 06/12/2001 | US6245996 Electrical interconnect structure having electromigration-inhibiting segments |
| 06/12/2001 | US6245992 IC chip security box |
| 06/12/2001 | US6245930 Chemical-sensitization resist composition |
| 06/12/2001 | US6245692 Method to selectively heat semiconductor wafers |
| 06/12/2001 | US6245691 Forming trench isolation regions within isolation trenches of microelectronics integrated circuits |
| 06/12/2001 | US6245690 Method of improving moisture resistance of low dielectric constant films |
| 06/12/2001 | US6245689 Annealing silicon wafer substrate in a heated gaseous nitric oxide ambient, evacuation of gas and annealing substrate in a different oxidizing gas ambient to yield a silicon oxynitride diffusion barrier having a gradient nitrogen concentration |
| 06/12/2001 | US6245688 Dry Air/N2 post treatment to avoid the formation of B/P precipitation after BPSG film deposition |
| 06/12/2001 | US6245687 Precision wide band gap semiconductor etching |
| 06/12/2001 | US6245686 Process for forming a semiconductor device and a process for operating an apparatus |
| 06/12/2001 | US6245685 Method for forming a square oxide structure or a square floating gate structure without rounding effect |
| 06/12/2001 | US6245684 Method of obtaining a rounded top trench corner for semiconductor trench etch applications |
| 06/12/2001 | US6245683 Stress relieve pattern for damascene process |
| 06/12/2001 | US6245682 Forming protective dielectric oxide layer on side walls of photolithographically formed submicron polysilicon gate features and then selectively wet etching silicon oxynitride antireflection coating (arc) using hot phosphoric acid |
| 06/12/2001 | US6245681 Dual temperature nitride strip process |
| 06/12/2001 | US6245679 Apparatus and methods for chemical-mechanical polishing of semiconductor wafers |
| 06/12/2001 | US6245678 Method for manufacturing semiconductor wafers |
| 06/12/2001 | US6245677 Backside chemical etching and polishing |
| 06/12/2001 | US6245676 Method of electroplating copper interconnects |
| 06/12/2001 | US6245675 Partially filling with aluminum the via holes through a dielectric layer to contact aluminum printed circuit lines the plugging with tungsten whereby the aluminum replenishes electrons lost through electromigration |
| 06/12/2001 | US6245674 Method of forming a metal silicide comprising contact over a substrate |
| 06/12/2001 | US6245673 Method of forming tungsten silicide film |
| 06/12/2001 | US6245672 Forming a metal film on doped region of a semiconductor body surface, carbiding or oxycarbiding the metal film surface by introducing carbon and/or oxygen and heat treating to densify, overcoating with copper metallization |
| 06/12/2001 | US6245671 Semiconductor processing method of forming an electrically conductive contact plug |
| 06/12/2001 | US6245670 Method for filling a dual damascene opening having high aspect ratio to minimize electromigration failure |
| 06/12/2001 | US6245669 High selectivity Si-rich SiON etch-stop layer |
| 06/12/2001 | US6245668 Sputtered tungsten diffusion barrier for improved interconnect robustness |
| 06/12/2001 | US6245667 Method of forming via |
| 06/12/2001 | US6245666 Method for forming a delamination resistant multi-layer dielectric layer for passivating a conductor layer |
| 06/12/2001 | US6245665 Semiconductor device and method of fabricating the same |
| 06/12/2001 | US6245664 Method and system of interconnecting conductive elements in an integrated circuit |
| 06/12/2001 | US6245663 IC interconnect structures and methods for making same |
| 06/12/2001 | US6245662 Method of producing an interconnect structure for an integrated circuit |
| 06/12/2001 | US6245660 Process for production of semiconductor device having contact plugs with reduced leakage current |
| 06/12/2001 | US6245659 Semiconductor device and method for manufacturing the same |
| 06/12/2001 | US6245658 Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system |
| 06/12/2001 | US6245657 Self-aligned, low contact resistance, via fabrication process |
| 06/12/2001 | US6245656 Method for producing multi-level contacts |
| 06/12/2001 | US6245655 Method for planarized deposition of a material |
| 06/12/2001 | US6245654 Method for preventing tungsten contact/via plug loss after a backside pressure fault |
| 06/12/2001 | US6245653 Method of filling an opening in an insulating layer |
| 06/12/2001 | US6245652 Method of forming ultra thin gate dielectric for high performance semiconductor devices |
| 06/12/2001 | US6245651 Method of simultaneously forming a line interconnect and a borderless contact to diffusion |
| 06/12/2001 | US6245650 Process for production of semiconductor device |
| 06/12/2001 | US6245649 Method for forming a retrograde impurity profile |
| 06/12/2001 | US6245647 Method for fabrication of thin film |
| 06/12/2001 | US6245646 Film frame substrate fixture |
| 06/12/2001 | US6245645 Method of fabricating an SOI wafer |
| 06/12/2001 | US6245644 Methods of forming field oxide and active area regions on a semiconductive substrate |
| 06/12/2001 | US6245643 Method of removing polysilicon residual in a LOCOS isolation process using an etching selectivity solution |
| 06/12/2001 | US6245642 Process for planarizing buried oxide films in trenches by applying sequential diverse CMP treatments |
| 06/12/2001 | US6245641 Semiconductor device comprising trench isolation insulator film and method of fabricating the same |
| 06/12/2001 | US6245640 Etching support through mask comprising a doped silicon oxide layer covered with an antireflection layer formed in two vapor deposition steps without vacuum interruption, removing mask with a hydrogen fluoride/ethylene glycol solution |
| 06/12/2001 | US6245639 Method to reduce a reverse narrow channel effect for MOSFET devices |
| 06/12/2001 | US6245638 Trench and gate dielectric formation for semiconductor devices |
| 06/12/2001 | US6245637 STI process |
| 06/12/2001 | US6245636 Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate |
| 06/12/2001 | US6245635 Method of fabricating shallow trench isolation |
| 06/12/2001 | US6245633 Fabrication method for a double-side double-crown stacked capacitor |
| 06/12/2001 | US6245632 Variable temperature methods of forming hemispherical grained silicon (HSG-Si) layers |
| 06/12/2001 | US6245631 Method of forming buried bit line memory circuitry and semiconductor processing method of forming a conductive line |
| 06/12/2001 | US6245630 Spherical shaped semiconductor integrated circuit |
| 06/12/2001 | US6245629 Semiconductor structures and manufacturing methods |
| 06/12/2001 | US6245628 Method of manufacturing a resistor in a semiconductor device |
| 06/12/2001 | US6245627 Method of fabricating a load resistor for an SRAM |
| 06/12/2001 | US6245626 Method of fabricating a MOS device using a sacrificial layer and spacer |
| 06/12/2001 | US6245625 Fabrication method of a self-aligned contact window |
| 06/12/2001 | US6245624 Methods of fabricating field effect transistors by first forming heavily doped source/drain regions and then forming lightly doped source/drain regions |
| 06/12/2001 | US6245623 CMOS semiconductor device containing N-channel transistor having shallow LDD junctions |
| 06/12/2001 | US6245622 Doping active region of integrated circuit surface at an oblique angle to form amorphous structure, coating with metal film and heat treating to form metal silicide |
| 06/12/2001 | US6245621 Semiconductor device manufacturing method |
| 06/12/2001 | US6245620 Method for foaming MOS transistor having bi-layered spacer |
| 06/12/2001 | US6245619 Disposable-spacer damascene-gate process for SUB 0.05 μm MOS devices |
| 06/12/2001 | US6245618 Mosfet with localized amorphous region with retrograde implantation |
| 06/12/2001 | US6245617 Method of fabricating dielectric layer |
| 06/12/2001 | US6245616 Method of forming oxynitride gate dielectric |
| 06/12/2001 | US6245615 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction |
| 06/12/2001 | US6245614 Method of manufacturing a split-gate flash memory cell with polysilicon spacers |
| 06/12/2001 | US6245613 Field effect transistor having a floating gate |
| 06/12/2001 | US6245612 Method for making the bottom electrode of a capacitor |
| 06/12/2001 | US6245611 Process for manufacturing semiconductor integrated circuit device |
| 06/12/2001 | US6245610 Method of protecting a well at a floating stage |
| 06/12/2001 | US6245609 High voltage transistor using P+ buried layer |
| 06/12/2001 | US6245608 Ion implantation process for forming contact regions in semiconductor materials |
| 06/12/2001 | US6245606 Forming a temporary aluminum thin film on heated, clean, atomically flat silicon surface of semiconductor integrated circuit, uniformly oxidizing aluminum in an ozone atmosphere to form a thin gate dielectric film |
| 06/12/2001 | US6245605 Method to protect metal from oxidation during poly-metal gate formation in semiconductor device manufacturing |
| 06/12/2001 | US6245604 Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits |
| 06/12/2001 | US6245603 Manufacturing method for semiconductor device |
| 06/12/2001 | US6245602 Top gate self-aligned polysilicon TFT and a method for its production |
| 06/12/2001 | US6245600 Method and structure for SOI wafers to avoid electrostatic discharge |
| 06/12/2001 | US6245599 Circuit wiring system circuit wiring method semi-conductor package and semi-conductor package substrate |
| 06/12/2001 | US6245597 Method for reducing die cracking in integrated circuits |
| 06/12/2001 | US6245596 Method of producing semiconductor device with heat dissipation metal layer and metal projections |
| 06/12/2001 | US6245595 Techniques for wafer level molding of underfill encapsulant |
| 06/12/2001 | US6245594 Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly |
| 06/12/2001 | US6245593 Semiconductor device with flat protective adhesive sheet and method of manufacturing the same |
| 06/12/2001 | US6245585 Method of providing levelling and focusing adjustments on a semiconductor wafer |
| 06/12/2001 | US6245583 Low stress method and apparatus of underfilling flip-chip electronic devices |
| 06/12/2001 | US6245582 Process for manufacturing semiconductor device and semiconductor component |
| 06/12/2001 | US6245581 Method and apparatus for control of critical dimension using feedback etch control |