| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 06/26/2001 | US6251789 Selective slurries for the formation of conductive structures |
| 06/26/2001 | US6251788 Planarizing surface |
| 06/26/2001 | US6251787 Elimination of photo-induced electrochemical dissolution in chemical mechanical polishing |
| 06/26/2001 | US6251786 Method to create a copper dual damascene structure with less dishing and erosion |
| 06/26/2001 | US6251785 Apparatus and method for polishing a semiconductor wafer in an overhanging position |
| 06/26/2001 | US6251784 Real-time control of chemical-mechanical polishing processing by monitoring ionization current |
| 06/26/2001 | US6251783 Method of manufacturing shallow trench isolation |
| 06/26/2001 | US6251781 Method to deposit a platinum seed layer for use in selective copper plating |
| 06/26/2001 | US6251780 Method for fabricating thin film at high temperature |
| 06/26/2001 | US6251779 Method of forming a self-aligned silicide on a semiconductor wafer |
| 06/26/2001 | US6251778 Method for using CMP process in a salicide process |
| 06/26/2001 | US6251777 Thermal annealing method for forming metal silicide layer |
| 06/26/2001 | US6251776 Plasma treatment to reduce stress corrosion induced voiding of patterned metal layers |
| 06/26/2001 | US6251775 Self-aligned copper silicide formation for improved adhesion/electromigration |
| 06/26/2001 | US6251774 Method of manufacturing a semiconductor device |
| 06/26/2001 | US6251772 Dielectric adhesion enhancement in damascene process for semiconductors |
| 06/26/2001 | US6251771 Hydrogen passivation of chemical-mechanically polished copper-containing layers |
| 06/26/2001 | US6251770 Dual-damascene dielectric structures and methods for making the same |
| 06/26/2001 | US6251769 Method of manufacturing contact pad |
| 06/26/2001 | US6251768 Method of arranging the staggered shape bond pads layers for effectively reducing the size of a die |
| 06/26/2001 | US6251767 Ball grid assembly with solder columns |
| 06/26/2001 | US6251766 Method for improving attachment reliability of semiconductor chips and modules |
| 06/26/2001 | US6251765 Manufacturing metal dip solder bumps for semiconductor devices |
| 06/26/2001 | US6251764 Method to form an L-shaped silicon nitride sidewall spacer |
| 06/26/2001 | US6251763 Semiconductor device and method for manufacturing same |
| 06/26/2001 | US6251762 Method and device for improved salicide resistance on polysilicon gates |
| 06/26/2001 | US6251761 Process for polycrystalline silicon gates and high-K dielectric compatibility |
| 06/26/2001 | US6251760 Semiconductor device and its wiring and a fabrication method thereof |
| 06/26/2001 | US6251759 Method and apparatus for depositing material upon a semiconductor wafer using a transition chamber of a multiple chamber semiconductor wafer processing system |
| 06/26/2001 | US6251758 Construction of a film on a semiconductor wafer |
| 06/26/2001 | US6251757 Formation of highly activated shallow abrupt junction by thermal budget engineering |
| 06/26/2001 | US6251756 Furnace for continuous, high throughput diffusion processes from various diffusion sources |
| 06/26/2001 | US6251755 High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe |
| 06/26/2001 | US6251754 Semiconductor substrate manufacturing method |
| 06/26/2001 | US6251753 Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition |
| 06/26/2001 | US6251751 Bulk and strained silicon on insulator using local selective oxidation |
| 06/26/2001 | US6251750 Method for manufacturing shallow trench isolation |
| 06/26/2001 | US6251749 Shallow trench isolation formation with sidewall spacer |
| 06/26/2001 | US6251748 Method of manufacturing shallow trench isolation structure |
| 06/26/2001 | US6251747 Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices |
| 06/26/2001 | US6251746 Methods of forming trench isolation regions having stress-reducing nitride layers therein |
| 06/26/2001 | US6251745 Two-dimensional scaling method for determining the overlay error and overlay process window for integrated circuits |
| 06/26/2001 | US6251744 Implant method to improve characteristics of high voltage isolation and high voltage breakdown |
| 06/26/2001 | US6251743 Method of liquid treatment of microstructures comprising bendable structural members |
| 06/26/2001 | US6251742 Method of manufacturing a cup-shape capacitor |
| 06/26/2001 | US6251741 Method of manufacturing a semiconductor device |
| 06/26/2001 | US6251740 Method of forming and electrically connecting a vertical interdigitated metal-insulator-metal capacitor extending between interconnect layers in an integrated circuit |
| 06/26/2001 | US6251739 Integrated circuit, components thereof and manufacturing method |
| 06/26/2001 | US6251738 Process for forming a silicon-germanium base of heterojunction bipolar transistor |
| 06/26/2001 | US6251737 Method of increasing gate surface area for depositing silicide material |
| 06/26/2001 | US6251736 Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arrays |
| 06/26/2001 | US6251735 Method of forming shallow trench isolation structure |
| 06/26/2001 | US6251734 Method for fabricating trench isolation and trench substrate contact |
| 06/26/2001 | US6251732 Method and apparatus for forming self-aligned code structures for semi conductor devices |
| 06/26/2001 | US6251731 Method for fabricating high-density and high-speed nand-type mask roms |
| 06/26/2001 | US6251730 Semiconductor power device manufacture |
| 06/26/2001 | US6251729 Method of manufacturing a nonvolatile memory |
| 06/26/2001 | US6251728 Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions |
| 06/26/2001 | US6251727 Method of making select gate self-aligned to floating for split gate flash memory structure |
| 06/26/2001 | US6251726 Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillar |
| 06/26/2001 | US6251725 Method of fabricating a DRAM storage node on a semiconductor wafer |
| 06/26/2001 | US6251724 Method to increase the clear ration of capacitor silicon nitride to improve the threshold voltage uniformity |
| 06/26/2001 | US6251723 Method for manufacturing semiconductor memory device capable of improving isolation characteristics |
| 06/26/2001 | US6251722 Method of fabricating a trench capacitor |
| 06/26/2001 | US6251721 Semiconductor device and method of manufacturing the same |
| 06/26/2001 | US6251720 High pressure reoxidation/anneal of high dielectric constant materials |
| 06/26/2001 | US6251719 Poly gate process that provides a novel solution to fix poly-2 residue under poly-1 oxide for charge coupled devices |
| 06/26/2001 | US6251718 Method for manufacturing semiconductor device |
| 06/26/2001 | US6251717 Viable memory cell formed using rapid thermal annealing |
| 06/26/2001 | US6251716 JFET structure and manufacture method for low on-resistance and low voltage application |
| 06/26/2001 | US6251715 Thin film transistor-liquid crystal display and a manufacturing method thereof |
| 06/26/2001 | US6251714 Method of making thin film field effect transistors |
| 06/26/2001 | US6251713 Method of making an SRAM storage cell with N channel thin film transistor load devices |
| 06/26/2001 | US6251712 Method of using phosphorous to getter crystallization catalyst in a p-type device |
| 06/26/2001 | US6251711 Method for forming bridge free silicide |
| 06/26/2001 | US6251710 Method of making a dual damascene anti-fuse with via before wire |
| 06/26/2001 | US6251707 Electrically connecting semiconductor chip to wiring surfaceusing pattern |
| 06/26/2001 | US6251705 Low profile integrated circuit packages |
| 06/26/2001 | US6251704 Method of manufacturing semiconductor devices having solder bumps with reduced cracks |
| 06/26/2001 | US6251703 CMS coated microelectronic component and its method of manufacture |
| 06/26/2001 | US6251702 Use of an oxide surface to facilitate gate break on a carrier substrate for a semiconductor device |
| 06/26/2001 | US6251697 Non-contact method for monitoring and controlling plasma charging damage in a semiconductor device |
| 06/26/2001 | US6251696 Method of forming integrated circuit with evaluation contacts electrically connected by forming via holes through the chip, and bonding the chip with a substrate |
| 06/26/2001 | US6251695 Multichip module packaging process for known good die burn-in |
| 06/26/2001 | US6251694 Method of testing and packaging a semiconductor chip |
| 06/26/2001 | US6251693 Semiconductor processing methods and semiconductor defect detection methods |
| 06/26/2001 | US6251692 Semiconductor processing workpiece support with sensory subsystem for detection of wafers or other semiconductor workpieces |
| 06/26/2001 | US6251569 Forming a pattern of a negative photoresist |
| 06/26/2001 | US6251568 Methods and apparatus for stripping photoresist and polymer layers from a semiconductor stack in a non-corrosive environment |
| 06/26/2001 | US6251567 Process for manufacturing microstructured bodies |
| 06/26/2001 | US6251560 Photoresist compositions with cyclic olefin polymers having lactone moiety |
| 06/26/2001 | US6251551 Adjustment in vertical plane; tilting |
| 06/26/2001 | US6251550 Maskless photolithography system that digitally shifts mask data responsive to alignment data |
| 06/26/2001 | US6251544 Positioning a mask; exposure to light; calibration of pattern |
| 06/26/2001 | US6251542 Semiconductor wafer etching method |
| 06/26/2001 | US6251541 Shaping a charged particle beam |
| 06/26/2001 | US6251528 Method to plate C4 to copper stud |
| 06/26/2001 | US6251501 Surface mount circuit device and solder bumping method therefor |
| 06/26/2001 | US6251488 Precision spray processes for direct write electronic components |
| 06/26/2001 | US6251487 Method for coating a resist film |