Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2002
04/30/2002US6381005 Mask holding device, exposure apparatus and device manufacturing method
04/30/2002US6381002 Process for controlling a gap between a mask and a workpiece in proximity exposure and a proximity exposure device
04/30/2002US6380799 Internal voltage generation circuit having stable operating characteristics at low external supply voltages
04/30/2002US6380795 Semiconductor integrated circuit
04/30/2002US6380792 Semiconductor integrated circuit
04/30/2002US6380768 Display device capable of collecting substantially all power charged to capacitive load in display panel
04/30/2002US6380765 Double pass transistor logic with vertical gate transistors
04/30/2002US6380764 Semiconductor integrated circuit device, recording medium stored with cell library, and method for designing semiconductor integrated circuit
04/30/2002US6380756 Burin carrier and semiconductor die assembly
04/30/2002US6380754 Removable electrical interconnect apparatuses including an engagement proble
04/30/2002US6380753 Screening method of semiconductor device and apparatus thereof
04/30/2002US6380751 Wafer probe station having environment control enclosure
04/30/2002US6380684 Plasma generating apparatus and semiconductor manufacturing method
04/30/2002US6380636 Nonvolatile semiconductor memory device having an array structure suitable to high-density integrationization
04/30/2002US6380635 Apparatus and methods for coupling conductive leads of semiconductor assemblies
04/30/2002US6380634 Conductor wires and semiconductor device using them
04/30/2002US6380632 Center bond flip-chip semiconductor device and method of making it
04/30/2002US6380631 Apparatus and methods of packaging and testing die
04/30/2002US6380629 Wafer level stack package and method of fabricating the same
04/30/2002US6380628 Microstructure liner having improved adhesion
04/30/2002US6380627 Low resistance barrier layer for isolating, adhering, and passivating copper metal in semiconductor fabrication
04/30/2002US6380626 Semiconductor device for attachment to a semiconductor substrate
04/30/2002US6380622 Electric apparatus having a contact intermediary member and method for manufacturing the same
04/30/2002US6380621 Semiconductor device and manufacturing method thereof
04/30/2002US6380620 Tape ball grid array semiconductor
04/30/2002US6380618 Fabrication of integrated circuits on both sides of a semiconductor wafer
04/30/2002US6380615 Chip size stack package, memory module having the same, and method of fabricating the module
04/30/2002US6380613 Semiconductor device
04/30/2002US6380612 Thin film formed by inductively coupled plasma
04/30/2002US6380611 Treatment for film surface to reduce photo footing
04/30/2002US6380610 Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect
04/30/2002US6380609 Silicided undoped polysilicon for capacitor bottom plate
04/30/2002US6380607 Semiconductor device and method for reducing parasitic capacitance between data lines
04/30/2002US6380606 Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same
04/30/2002US6380602 Semiconductor device
04/30/2002US6380601 Multilayer semiconductor structure with phosphide-passivated germanium substrate
04/30/2002US6380599 Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination
04/30/2002US6380598 Radiation hardened semiconductor memory
04/30/2002US6380596 Method of forming a local interconnect, method of fabricating integrated circuitry comprising an sram cell having a local interconnect and having circuitry peripheral to the sram cell, and method of forming contact plugs
04/30/2002US6380595 Semiconductor device and manufacturing method therefor
04/30/2002US6380594 Semiconductor device
04/30/2002US6380590 SOI chip having multiple threshold voltage MOSFETs by using multiple channel materials and method of fabricating same
04/30/2002US6380589 Semiconductor-on-insulator (SOI) tunneling junction transistor SRAM cell
04/30/2002US6380588 Semiconductor device having uniform spacers
04/30/2002US6380587 Semiconductor read-only memory device and method of fabricating the same
04/30/2002US6380585 Nonvolatile semiconductor device capable of increased electron injection efficiency
04/30/2002US6380584 Semiconductor memory device with single and double sidewall spacers
04/30/2002US6380583 Method to increase coupling ratio of source to floating gate in split-gate flash
04/30/2002US6380582 Autoaligned etching process for realizing word lines in memory devices integrated semiconductor substrates
04/30/2002US6380581 DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors
04/30/2002US6380580 Method of making a thin film capacitor with an improved top electrode
04/30/2002US6380579 Capacitor of semiconductor device
04/30/2002US6380578 High-speed stacked capacitor in SOI structure
04/30/2002US6380576 Selective polysilicon stud growth
04/30/2002US6380575 DRAM trench cell
04/30/2002US6380574 Ferroelectric capacitor with a self-aligned diffusion barrier
04/30/2002US6380573 Substrate with channel; ferroelectric dielectric; barrier electrode
04/30/2002US6380569 High power unipolar FET switch
04/30/2002US6380567 Semiconductor device and fabrication method thereof
04/30/2002US6380561 Semiconductor device and process for producing the same
04/30/2002US6380560 Semiconductor device forming a pixel matrix circuit
04/30/2002US6380559 Thin film transistor array substrate for a liquid crystal display
04/30/2002US6380558 Semiconductor device and method of fabricating the same
04/30/2002US6380557 Test chip for evaluating fillers of molding material with dams formed on a semiconductor substrate to define slits for capturing the fillers
04/30/2002US6380556 Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure
04/30/2002US6380551 Optical function device with photonic band gap and/or filtering characteristics
04/30/2002US6380518 Heat treatment apparatus and substrate processing system
04/30/2002US6380506 Use of hot carrier effects to trim analog transistor pair
04/30/2002US6380492 Contact film used for devices having ball grid array structure and device mounting structure
04/30/2002US6380479 Photovoltaic element and method for manufacture thereof
04/30/2002US6380271 Mixing a polybenzoxazole precursor or a polybenzoxazole resin with an oligomer, forming film from resulting mixture, heating film in nitrogen containing oxygen to give rise to thermal decomposition and gasification of oligomer to form resin layer
04/30/2002US6380108 Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby
04/30/2002US6380106 Forming spaced conductive lines over a semiconductor structure; forming filler material over conductive lines and semiconductor structure; forming permeable dielectric layer; vaporizing filler material; depositing insulating layer
04/30/2002US6380105 Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates
04/30/2002US6380104 Method for forming composite gate dielectric layer equivalent to silicon oxide gate dielectric layer
04/30/2002US6380103 Rapid thermal etch and rapid thermal oxidation
04/30/2002US6380102 Method for fabricating gate oxide film of semiconductor device
04/30/2002US6380100 Semiconductor processing apparatuses, and methods of forming antireflective coating materials over substrates
04/30/2002US6380099 Porous region removing method and semiconductor substrate manufacturing method
04/30/2002US6380098 Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
04/30/2002US6380097 Method for obtaining a sulfur-passivated semiconductor surface
04/30/2002US6380096 In-situ integrated oxide etch process particularly useful for copper dual damascene
04/30/2002US6380095 Silicon trench etch using silicon-containing precursors to reduce or avoid mask erosion
04/30/2002US6380094 Method for preventing redeposition of etching products onto substrate surfaces during a tungsten re-etching process in the production of LSI circuits
04/30/2002US6380092 Gas phase planarization process for semiconductor wafers
04/30/2002US6380091 Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer
04/30/2002US6380090 Protecting method applied to the semiconductor manufacturing process
04/30/2002US6380089 Method of manufacturing semiconductor device
04/30/2002US6380088 Method to form a recessed source drain on a trench side wall with a replacement gate technique
04/30/2002US6380087 CMP process utilizing dummy plugs in damascene process
04/30/2002US6380085 Method of manufacturing semiconductor devices
04/30/2002US6380084 Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
04/30/2002US6380083 Process for semiconductor device fabrication having copper interconnects
04/30/2002US6380082 Method of fabricating Cu interconnects with reduced Cu contamination
04/30/2002US6380081 Method of vaporizing liquid sources and apparatus therefor
04/30/2002US6380080 Methods for preparing ruthenium metal films
04/30/2002US6380079 Metal wiring in semiconductor device and method for fabricating the same
04/30/2002US6380078 Method for fabrication of damascene interconnects and related structures
04/30/2002US6380077 Method of forming contact opening
04/30/2002US6380076 Dielectric filling of electrical wiring planes