Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2002
04/30/2002US6380075 Method for forming an open-bottom liner for a conductor in an electronic structure and device formed
04/30/2002US6380074 Deposition of various base layers for selective layer growth in semiconductor production
04/30/2002US6380073 Method for forming metal interconnection structure without corner faceted
04/30/2002US6380072 Metallizing process of semiconductor industry
04/30/2002US6380071 Method of fabricating semiconductor device
04/30/2002US6380070 Semiconductor device having a dual damascene interconnect structure and method for manufacturing same
04/30/2002US6380069 Method of removing micro-scratch on metal layer
04/30/2002US6380068 Method for planarizing a flash memory device
04/30/2002US6380067 Method for creating partially UV transparent anti-reflective coating for semiconductors
04/30/2002US6380066 Methods for eliminating metal corrosion by FSG
04/30/2002US6380065 Interconnection structure and fabrication process therefor
04/30/2002US6380064 Semiconductor devices and process for producing the same
04/30/2002US6380063 Raised wall isolation device with spacer isolated contacts and the method of so forming
04/30/2002US6380062 Method of fabricating semiconductor package having metal peg leads and connected by trace lines
04/30/2002US6380061 Process for fabricating bump electrode
04/30/2002US6380060 Off-center solder ball attach and methods therefor
04/30/2002US6380058 Method and apparatus for manufacturing semiconductor device
04/30/2002US6380057 Enhancement of nickel silicide formation by use of nickel pre-amorphizing implant
04/30/2002US6380056 Lightly nitridation surface for preparing thin-gate oxides
04/30/2002US6380055 Dopant diffusion-retarding barrier region formed within polysilicon gate layer
04/30/2002US6380053 Method for producing a semiconductor device with an accurately controlled impurity concentration profile in the extension regions
04/30/2002US6380052 Growing p-type compound semiconductor film; heating; cooling; continuously decreasing the ambient temperature from second specific temperature to initial temperature
04/30/2002US6380051 Growth promoting film is partially formed on a substrate having a portion which acts as a growth suppressing film on a surface thereof, and a nitride compound semiconductor film of a single crystal is grown thereon.
04/30/2002US6380050 Method of epitaxially growing a GaN semiconductor layer
04/30/2002US6380049 Semiconductor substrate and method of manufacturing semiconductor device
04/30/2002US6380048 Die paddle enhancement for exposed pad in semiconductor packaging
04/30/2002US6380047 Shallow trench isolation formation with two source/drain masks and simplified planarization mask
04/30/2002US6380046 Method of manufacturing a semiconductor device
04/30/2002US6380045 Method of forming asymmetric wells for DRAM cells
04/30/2002US6380044 High-speed semiconductor transistor and selective absorption process forming same
04/30/2002US6380043 Low temperature process to form elevated drain and source of a field effect transistor having high-K gate dielectric
04/30/2002US6380042 Self-aligned contact process using stacked spacers
04/30/2002US6380041 Semiconductor with laterally non-uniform channel doping profile and manufacturing method therefor
04/30/2002US6380040 Prevention of dopant out-diffusion during silicidation and junction formation
04/30/2002US6380039 Method for forming a FET having L-shaped insulating spacers
04/30/2002US6380038 Transistor with electrically induced source/drain extensions
04/30/2002US6380037 Method of manufacturing a semiconductor integrated circuit device
04/30/2002US6380036 Semiconductor device and method of manufacturing the same
04/30/2002US6380035 Poly tip formation and self-align source process for split-gate flash cell
04/30/2002US6380034 Process for manufacturing memory cells with dimensional control of the floating gate regions
04/30/2002US6380033 Growing oxide layer over substrate, removing a portion of first oxide layer in flash memory cell area of the substrate; growing a second oxide layer; annealing first oxide layer and second oxide layer; depositing in situ doped amorphous silicon
04/30/2002US6380032 Flash memory device and method of making same
04/30/2002US6380031 Method to form an embedded flash memory circuit with reduced process steps
04/30/2002US6380030 Implant method for forming Si3N4 spacer
04/30/2002US6380029 Method of forming ono stacked films and DCS tungsten silicide gate to improve polycide gate performance for flash memory devices
04/30/2002US6380028 Semiconductor device and a method of manufacturing thereof
04/30/2002US6380027 Dual tox trench dram structures and process using V-groove
04/30/2002US6380026 Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
04/30/2002US6380025 Method of encapsulating a photovoltaic module by an encapsulating material and the photovoltaic module
04/30/2002US6380024 Method of fabricating an SRAM cell featuring dual silicide gates and four buried contact regions
04/30/2002US6380023 Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits
04/30/2002US6380022 Method for creating a useful biopolar junction transistor from a parasitic bipolar junction transistor on a MOSFET
04/30/2002US6380021 Ultra-shallow junction formation by novel process sequence for PMOSFET
04/30/2002US6380020 Method for fabricating a semiconductor device having a device isolation insulating film
04/30/2002US6380019 Method of manufacturing a transistor with local insulator structure
04/30/2002US6380018 Semiconductor device and method for the production thereof
04/30/2002US6380017 Polysilicon-edge, base-emitter super self-aligned, low-power, high-frequency bipolar transistor and method of forming the transistor
04/30/2002US6380016 Method for forming programmable CMOS ROM devices
04/30/2002US6380015 Aoped polysilicon layer is formed over a silicon or silicon oxide substrate, and is counterdoped with boron to adjust work function
04/30/2002US6380014 Manufacture method of semiconductor device with suppressed impurity diffusion from gate electrode
04/30/2002US6380013 Method for forming semiconductor device having epitaxial channel layer using laser treatment
04/30/2002US6380012 Boron difluoride plasma doping method for forming ultra-shallow junction
04/30/2002US6380011 Semiconductor device and a method of manufacturing the same
04/30/2002US6380010 Shielded channel transistor structure with embedded source/drain junctions
04/30/2002US6380009 Method of manufacturing thin film transistors
04/30/2002US6380008 Edge stress reduction by noncoincident layers
04/30/2002US6380007 Semiconductor device and manufacturing method of the same
04/30/2002US6380006 Infiltrating solution of organic solvent into film and reflowing, etching exposed region using film as mask
04/30/2002US6380005 Charge transfer device and method for manufacturing the same
04/30/2002US6380004 Process for manufacturing radhard power integrated circuit
04/30/2002US6380003 Damascene anti-fuse with slot via
04/30/2002US6380000 Automatic recovery for die bonder wafer table wafermap operations
04/30/2002US6379999 Semiconductor device and method of manufacturing the same
04/30/2002US6379998 Semiconductor device and method for fabricating the same
04/30/2002US6379997 Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
04/30/2002US6379996 Package for semiconductor chip having thin recess portion and thick plane portion
04/30/2002US6379994 Pin-structure formed by laminating n-, i- and p-type semiconductor layers, each of which contains silicon atoms and has a non-monocrystalline crystal structure; hydrogen, helium or argon gas that contains 1 to 1000 ppm of oxygen
04/30/2002US6379991 Encapsulation methods for semiconductive die packages
04/30/2002US6379988 Pre-release plastic packaging of MEMS and IMEMS devices
04/30/2002US6379986 Anodizing a bulk aluminum material and then forming a tunnel oxidation film by irradiating oxygen
04/30/2002US6379985 Methods for cleaving facets in III-V nitrides grown on c-face sapphire substrates
04/30/2002US6379983 Automatically generating and storing a repair solution for muli-chip module (mcm), attaching a repair integrated circuit ic die to mcm, wire-bonding the reapir ic die in accordance with stored repair solution to repair mcm that fails testing
04/30/2002US6379982 Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
04/30/2002US6379981 Methods incorporating detectable atoms into etching processes
04/30/2002US6379980 Method and apparatus for monitoring material removal tool performance using endpoint time removal rate determination
04/30/2002US6379978 Memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and method for fabricating it
04/30/2002US6379977 Method of manufacturing ferroelectric memory device
04/30/2002US6379897 Methods for gene expression monitoring on electronic microarrays
04/30/2002US6379874 Using block copolymers as supercritical fluid developable photoresists
04/30/2002US6379872 Etching with fluorinated hydrocarbon gas through mask pattern; halting prior to underlayer exposure; etching with oxygen; semiconductors
04/30/2002US6379871 Method for fabricating a mask for a LIGA process
04/30/2002US6379870 Coating with dielectric, depositing photoresist, imagewise patterning and development, etching, cleaving across trenches; removal of oxidized portions with solvent; evaluation for defects
04/30/2002US6379869 Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterning
04/30/2002US6379868 Lithographic process for device fabrication using dark-field illumination
04/30/2002US6379862 Phenolic resins comprising methylolated bisphenols condensed with phenols; alkali-soluble resin, acid generator, and crosslinking agent; heat resistance; liquid crystal displays; semiconductors
04/30/2002US6379860 Positive photosensitive composition
04/30/2002US6379859 Positive photoresist composition and process for forming resist pattern using same
04/30/2002US6379851 Agglomerating flashes during energy beam lithography; defining cell upon impact of flash; writing subsequent flash; determination if termination; constructing library of standard cells; integrated circuits
04/30/2002US6379848 Generating photomask; cell includes test pattern and reference marker positioned to orient crosshair in microscope to evaluate degree of corner rounding; determination of pass/fail; semiconductors
04/30/2002US6379792 Silicone adhesive sheet and method for manufacturing