| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 06/06/2002 | US20020069349 Method and apparatus for control of semiconductor processing for reducing effects of environmental effects |
| 06/06/2002 | US20020069041 Semiconductor device simulation apparatus as well as method and storage medium storing simulation program thereof |
| 06/06/2002 | US20020069027 Arrangement and method of testing an integrated circuit |
| 06/06/2002 | US20020069025 Heat treatment apparatus, calibration method for temperature measuring system of the apparatus, and heat treatment system |
| 06/06/2002 | US20020069024 Method and apparatus for providing communication between a defect source identifier and a tool data collection and control system |
| 06/06/2002 | US20020068992 Self teaching robot |
| 06/06/2002 | US20020068989 Method and apparatus for designing integrated circuits and storage medium for storing the method |
| 06/06/2002 | US20020068982 Vacuum processing apparatus and semiconductor manafacturing line using the same |
| 06/06/2002 | US20020068803 High transparency at 193 nm wavelength, provides increased etching resistance; formed without 5-norbonen-2-carboxylate monomers which do not have offensive odors of the free acid |
| 06/06/2002 | US20020068685 Post plasma ashing wafer cleaning formulation |
| 06/06/2002 | US20020068684 Aliphatic C3-5 dicarboxylic acid corrosion inhibitor; hydrogen fluoride free; pH of at least 8.5 |
| 06/06/2002 | US20020068524 Clean room for semiconductor device |
| 06/06/2002 | US20020068517 Wafer polishing apparatus |
| 06/06/2002 | US20020068516 Apparatus and method for controlled delivery of slurry to a region of a polishing device |
| 06/06/2002 | US20020068513 Unsupported chemical mechanical polishing belt |
| 06/06/2002 | US20020068488 Stable electrical contact for silicon carbide devices |
| 06/06/2002 | US20020068469 Method for making a semiconductor device having a low-k dielectric layer |
| 06/06/2002 | US20020068468 (a) forming a p-type impurity doped compound semiconductor layer on the substrate; and (b) applying a microwave treatment over the p-type impurity doped compound semiconductor layer. |
| 06/06/2002 | US20020068467 Simultaneously flowing a plurality of reaction gases SiH4, N2, NH3, N2O into a chamber; and turning on a high frequency radio frequency power after some of said simultaneous flowing. |
| 06/06/2002 | US20020068466 Chemisorbing a first reactant adsorption layer combined with a halogen on a semiconductor substrate; removing the halogen with activated hydrogen gas; chemisorbing a second reactant into the first reactant adsorption layer |
| 06/06/2002 | US20020068465 Method of producing an oxidation-protected electrode for a capacitive electrode structure |
| 06/06/2002 | US20020068464 Pulsed-mode RF bias for side-wall coverage improvement |
| 06/06/2002 | US20020068463 Rapid chemical vapor deposition for spherical semiconductor processing |
| 06/06/2002 | US20020068462 Forming a carbon layer on at least a part of the material layer to prevent the part of the material layer from being etched; and wet-etching the material layer using an alkali solution. |
| 06/06/2002 | US20020068461 Method of fabricating wires for semiconductor devices |
| 06/06/2002 | US20020068460 Method of planarizing polysillicon plug |
| 06/06/2002 | US20020068459 Method for etching a semiconductor device |
| 06/06/2002 | US20020068458 Method for integrated in-situ cleaning and susequent atomic layer deposition within a single processing chamber |
| 06/06/2002 | US20020068456 Method and system to provide material removal and planarization employing a reactive pad |
| 06/06/2002 | US20020068455 Method for removing carbon-rich particles adhered on a copper surface |
| 06/06/2002 | US20020068454 Transition metal ions; chelating agents; surfactants; oxidizers; corrosion inhibitors; and water. |
| 06/06/2002 | US20020068453 Photoresist layer is photolithographically patterned to form holes which overlie interconnect areas; etched using Reactive Ion Etching to insulating layer; etched to stop layer; photoresist removed and antireflective layer etched |
| 06/06/2002 | US20020068452 Polishing agent and polishing method |
| 06/06/2002 | US20020068451 Semiconductor device production method |
| 06/06/2002 | US20020068450 Method for chemical mechanical polishing |
| 06/06/2002 | US20020068449 Method of depositing a copper seed layer which promotes improved feature surface coverage |
| 06/06/2002 | US20020068448 Electron emitter substrate comprising emitters having at least a partial covering comprising aluminum nitride; and an electrode collector substrate spaced from the electron emitter substrate. |
| 06/06/2002 | US20020068447 Method of forming a pattern for a semiconductor device |
| 06/06/2002 | US20020068446 Method of forming self-aligned silicide layer |
| 06/06/2002 | US20020068445 First coat of the adhesion layer has a thickness on the bottom greater than the thickness on the sidewall. To compensate, a second coat is deposited that is thicker on the sidewalls that on the bottom |
| 06/06/2002 | US20020068444 Dual layer silicide formation using an aluminum barrier to reduce surface roughness at silicide/junction interface |
| 06/06/2002 | US20020068443 Semiconductor device and method of fabricating the same |
| 06/06/2002 | US20020068442 Opening of a downwardly protruding window for a dual damascene structure |
| 06/06/2002 | US20020068441 Top layers of metal for high performance IC's |
| 06/06/2002 | US20020068440 Methods of fabricating buried digit lines and semiconductor devices including same |
| 06/06/2002 | US20020068439 Method of manufacturing flash memory |
| 06/06/2002 | US20020068438 Method for fabricating semiconductor devices |
| 06/06/2002 | US20020068437 Etching stop spacer is formed on each sidewall of the conductive wire; inter-metal dielectric layer is formed over the substrate patterned to form a via opening that exposes the conductive wire; metal plugging entire via hole |
| 06/06/2002 | US20020068436 Resist trim process to define small openings in dielectric layers |
| 06/06/2002 | US20020068435 Method for removing carbon-rich particles adhered on the exposed copper surface of a copper/low k dielectric dual damascene structure |
| 06/06/2002 | US20020068434 System for planarizing microelectronic substrates having apertures |
| 06/06/2002 | US20020068433 Barrier layer comprising titanium nitride over a topographical structure on a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. |
| 06/06/2002 | US20020068432 Method for patterning a dual damascene with retrograde implantation |
| 06/06/2002 | US20020068431 Encapsulated metal structures for semiconductor devices and MIM capacitors including the same |
| 06/06/2002 | US20020068430 Methods of forming void regions, dielectric regions and capacitor constructions |
| 06/06/2002 | US20020068429 Local interconnect structures and methods for making the same |
| 06/06/2002 | US20020068428 Semiconductor device and method of manufacturing the same |
| 06/06/2002 | US20020068427 Single step process for blanket-selective cvd aluminum deposition |
| 06/06/2002 | US20020068426 Microelectronic packages having deformed bonded leads and methods therefor |
| 06/06/2002 | US20020068425 Method for bumping and backlapping a semiconductor wafer |
| 06/06/2002 | US20020068424 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| 06/06/2002 | US20020068423 Contact forming method for semiconductor device |
| 06/06/2002 | US20020068422 Heat treatment apparatus and method of manufacturing a semiconductor device |
| 06/06/2002 | US20020068421 Method of fabricating a semiconductor device |
| 06/06/2002 | US20020068420 Method for making an integrated circuit device with dielectrically isolated tubs and related circuit |
| 06/06/2002 | US20020068419 Semiconductor article and method of manufacturing the same |
| 06/06/2002 | US20020068418 Method for producing soi wafers by delamination |
| 06/06/2002 | US20020068417 Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures |
| 06/06/2002 | US20020068416 Method for depositing an undopped silicate glass layer |
| 06/06/2002 | US20020068415 Method of fabricating a shallow trench isolation structure |
| 06/06/2002 | US20020068414 Semiconductor device having a dummy active region for controlling high density plasma chemical vapor deposition |
| 06/06/2002 | US20020068413 Process of manufacturing semiconductor device |
| 06/06/2002 | US20020068412 The electrodes are formed on an inner surface of the exposed lower capacitor electrode, reducing the likelihood of lower electrode breakage and shorting (e.g., stringer formation) during fabrication. electrode. |
| 06/06/2002 | US20020068411 Method for manufacturing diode subassemblies used in rectifier assemblies of engine driven generators |
| 06/06/2002 | US20020068410 Method of manufacturing low-leakage, high-performance device |
| 06/06/2002 | US20020068409 Method of reducing junction capacitance |
| 06/06/2002 | US20020068408 Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing |
| 06/06/2002 | US20020068407 MOS transistor fabrication method |
| 06/06/2002 | US20020068406 Semiconductor device and method of manufacturing the same |
| 06/06/2002 | US20020068405 Fabrication method for a semiconductor integrated circuit device |
| 06/06/2002 | US20020068404 Stable high voltage semiconductor device structure |
| 06/06/2002 | US20020068403 Manufacturing method of a gate-split flash memory |
| 06/06/2002 | US20020068402 Nonvolatile semiconductor memory and process for fabricating the same |
| 06/06/2002 | US20020068401 Novel method and structure for stacked DRAM capacitors and FETs for embedded DRAM circuits |
| 06/06/2002 | US20020068400 Self aligned trench and method of forming the same |
| 06/06/2002 | US20020068399 Negative Ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation |
| 06/06/2002 | US20020068398 Forms a spacer at the sidewall of a floating gate pattern to increase the surface area of the floating gate; increase a gate coupling ratio; reduce the distance between the floating gates to prohibit a seam phenomenon |
| 06/06/2002 | US20020068397 Stacked local interconnect structure and method of fabricating same |
| 06/06/2002 | US20020068396 Silicon wafer with embedded optoelectronic material for monolithic OEIC |
| 06/06/2002 | US20020068395 Double LDD devices for improved DRAM refresh |
| 06/06/2002 | US20020068394 Semiconductor device and fabrication process therefor |
| 06/06/2002 | US20020068393 Gate technology for strained surface channel and strained buried channel MOSFET devices |
| 06/06/2002 | US20020068392 Method for fabricating thin film transistor including crystalline silicon active layer |
| 06/06/2002 | US20020068391 Laser annealing system for crystallization of semiconductor layer and method of the same |
| 06/06/2002 | US20020068390 Method of forming semiconductor thin film and plastic substrate |
| 06/06/2002 | US20020068388 Semiconductor device and method of manufacturing the same |
| 06/06/2002 | US20020068387 Selective polysilicon stud growth |
| 06/06/2002 | US20020068386 Methods of forming physical vapor deposition target/backing plate assemblies |
| 06/06/2002 | US20020068385 Method for forming anchored bond pads in semiconductor devices and devices formed |
| 06/06/2002 | US20020068384 Enhancements in framed sheet processing |