Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2002
06/13/2002WO2002046975A2 Routing method and apparatus
06/13/2002WO2002046864A2 Automated wafer handling with graphic user interface
06/13/2002WO2002046843A1 Method of aligning a photolithographic mask to a crystal plane
06/13/2002WO2002046842A1 Assembly comprising a plurality of mask containers
06/13/2002WO2002046839A2 Laser plasma from metals and nano-size particles
06/13/2002WO2002046810A1 Semiconductor device and method for manufacture thereof
06/13/2002WO2002046507A2 Onium salts and the use therof as latent acids
06/13/2002WO2002046493A1 Method for producing noble metal thin film electrode for usli
06/13/2002WO2002046489A1 Method for integrated in-situ cleaning and subsequent atomic layer deposition within a single processing chamber
06/13/2002WO2002046363A2 Improved methods for gene expression monitoring on electronic microarrays
06/13/2002WO2002045871A1 System and method for modulated ion-induced atomic layer deposition (mii-ald)
06/13/2002WO2002045868A2 Patterned deposition using compressed carbon dioxide
06/13/2002WO2002045799A1 Freeform substrates and devices
06/13/2002WO2002045476A2 Apparatus and method for electrochemically depositing metal on a semiconductor workpiece
06/13/2002WO2002030173A3 Method and apparatus for communicating images, data, or other information in a defect source identifier
06/13/2002WO2002029849A3 System, apparatus, and method for processing wafer using single frequency rf power in plasma processing chamber
06/13/2002WO2002029391A3 Defect knowledge library
06/13/2002WO2002027800A3 Trench dmos transistor having lightly doped source structure
06/13/2002WO2002027061A3 Process chamber lid
06/13/2002WO2002025733A3 Non-volatile memory cell array and methods of forming
06/13/2002WO2002025695A3 Tunable focus ring for plasma processing
06/13/2002WO2002019408A3 Method of etching carbon-containing silicon oxide films
06/13/2002WO2002019391A3 Apparatus and method for floe of process gas in an ultra-clean environment
06/13/2002WO2002017337A3 LOWER THERMAL BUDGET SiON BARRIER FOR MIS TANOX STACK CAPACITOR
06/13/2002WO2002015278A3 Multigate semiconductor device and method of fabrication
06/13/2002WO2002015222A3 Use of pulsed voltage in a plasma reactor
06/13/2002WO2002011193A3 Process for photoresist descumming and stripping in semiconductor applications by nh3 plasma
06/13/2002WO2002009177A3 Power mosfet and method for forming same using a self-aligned body implant
06/13/2002WO2002009162A3 Heated substrate support assembly and method
06/13/2002WO2002009161A3 Process for cleaning ceramic articles
06/13/2002WO2002007221A3 Embedded decoupling capacitor
06/13/2002WO2002005331A3 Removable gripper pads
06/13/2002WO2002003456A3 Semiconductor device and method of formation
06/13/2002WO2002003455A3 Highly conformal titanium nitride deposition process for high aspect ratio structures
06/13/2002WO2001095378A3 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
06/13/2002WO2001088977A3 Method and device for array threshold voltage control by trapped charge in trench isolation
06/13/2002WO2001084130A3 A nanotube-based electron emission device and systems using the same
06/13/2002WO2001082356A3 Method and apparatus for controlling chemical interactions during planarization of microelectronic substrates
06/13/2002WO2001075944A3 Dry silylation plasma etch process
06/13/2002WO2001042994A3 Modification of integrated circuits
06/13/2002WO2000068982A9 Fabrication of ohmic contacts to inp using non- stoichiometric inp layers
06/13/2002US20020073391 Semiconductor device having dummy pattern
06/13/2002US20020073387 Embedding parasitic model for pi-fet layouts
06/13/2002US20020073381 Method for designing integrated circuit device
06/13/2002US20020073380 Block based design methodology with programmable components
06/13/2002US20020072872 Method for diagnosing process parameter variations from measurements in analog circuits
06/13/2002US20020072866 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture
06/13/2002US20020072579 Novel tertiary alcohol compounds having alicyclic structure
06/13/2002US20020072475 High purity niobium and products containing the same, and methods of making the same
06/13/2002US20020072314 Diaphragm for chemical mechanical polisher
06/13/2002US20020072313 Carrier head with local pressure control for a chemical mechanical polishing apparatus
06/13/2002US20020072312 Chemical mechanical polishing apparatus having a cleaner for cleaning a conditioning disc and method of conditioning a polishing pad of the apparatus
06/13/2002US20020072311 Method and apparatus for mechanical and chemical-mechanical planarization of microelectronic substrates with metal compound abrasives
06/13/2002US20020072310 Abrasive liquid feed apparatus, method for feeding additive to abrasive liquid feed apparatus, and polishing apparatus
06/13/2002US20020072309 Polishing method and polishing apparatus
06/13/2002US20020072301 Apparatus and method for detecting a work piece in an automatic processing apparatus
06/13/2002US20020072296 Abrasive article having a window system for polishing wafers, and methods
06/13/2002US20020072253 Method of removing an amorphous oxide from a monocrystalline surface
06/13/2002US20020072252 Process for production of thin film semiconductor thin film, semiconductor device, process for production of semiconductor thin film, and apparatus for production of semiconductor thin film
06/13/2002US20020072251 Method for manufacturing semiconductor device
06/13/2002US20020072250 Methods of manufacturing integrated circuit devices having an encapsulated insulation layer
06/13/2002US20020072249 Vapor deposition of source gases of silicon and carbon under conditions to increase the growth rate of silicon carbide and reducing the defects; controlling the partial pressures and ratios; semiconductors; thin films; ingots
06/13/2002US20020072248 Chemical vapor deposition of a heated mixture of a silane (SinH2n+2 n=1-3) gas and and fluorocarbon (CmF2m+2 m=1-3) gas; reduced RC delay time in integrated circuits; heat resistance
06/13/2002US20020072247 Oxidizing silicon carbide in nitrous oxide using a temperature profile of about 1200 degrees C
06/13/2002US20020072246 Method of forming a spin-on-glass insulation layer
06/13/2002US20020072245 Thin film of monocrystalline oxide formed on a bulk wafer monolithically integrated with a complementary metal oxide on a monocrystalline substrate and does not require cooling
06/13/2002US20020072244 Photo-assisted remote plasma apparatus and method
06/13/2002US20020072242 Method of forming a slope lateral structure
06/13/2002US20020072241 Multi-position load lock chamber
06/13/2002US20020072240 Plasma etching apparatus with focus ring and plasma etching method
06/13/2002US20020072239 Method for manufacturing solid-state imaging device
06/13/2002US20020072238 Chemical mechanical polishing method for slurry free fixed abrasive pads
06/13/2002US20020072237 Method for unpatterned resist etch back of shallow trench isolation refill insulator
06/13/2002US20020072236 Wafer surface protection method
06/13/2002US20020072235 Hydrofluoric acid, nitric acid and hexafluorosilicic acid in a concentration of <10% by weight
06/13/2002US20020072233 Semiconductor device and method of manufacturing the same
06/13/2002US20020072232 Method of Forming an Electrically Conductive Line
06/13/2002US20020072231 Method of forming a self-aligned silicide
06/13/2002US20020072230 Residue-free contact openings and methods for fabricating same
06/13/2002US20020072229 Depositing a selective contact of a metal silicide and then an interconnect barrier layer
06/13/2002US20020072228 Semiconductor conductive pattern formation method
06/13/2002US20020072227 Method for improving barrier properties of refractory metals/metal nitrides with a safer alternative to silane
06/13/2002US20020072226 Manufacturing method of a semiconductor device
06/13/2002US20020072225 Hard-mask etch process
06/13/2002US20020072224 Method for improving local interconnects of multi-level interconnects process
06/13/2002US20020072223 Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications
06/13/2002US20020072222 Method for preventing Cu cross contamination
06/13/2002US20020072221 Semiconductor device and method for manufacturing the same
06/13/2002US20020072220 1,3-dioxa-2-silacyclohydrocarbons and 1-oxa-2-silacyclo-hydrocarbons siloxane precursors react with the surface and forms a film
06/13/2002US20020072219 Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation
06/13/2002US20020072218 Surface treatment and capping layer process for producing a copper interface in a semiconductor device
06/13/2002US20020072217 Method for improving contact reliability in semiconductor devices
06/13/2002US20020072216 Polyimide substrate is formed with a solder bump, directly heating and compressing so the bump and solder pad are bound and connected electrically
06/13/2002US20020072215 Method for forming barrier layers for solder bumps
06/13/2002US20020072214 Semiconductor device and method of fabrication thereof, circuit board, and electronic equipment
06/13/2002US20020072213 Method of fabricating soldering balls for semiconductor encapsulation
06/13/2002US20020072212 Multilayer semiconductor supports comprising silicones, epoxy resins, acrylic polymers, polyurethane, polyesters, polybutadiene and/or blends having fillers particles such as alumina
06/13/2002US20020072211 Method of manufacturing semiconductor devices
06/13/2002US20020072210 Method for forming liner layer in sin spacer
06/13/2002US20020072209 Method of forming tungsten nitride layer as metal diffusion barrier in gate structure of MOSFET device
1 ... 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 ... 6590