Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2002
06/18/2002US6407420 Integrated circuit device having line width determined by side wall spacer provided in openings formed in insulating film for connection conductors
06/18/2002US6407419 Semiconductor device and manufacturing method thereof
06/18/2002US6407416 Semiconductor device
06/18/2002US6407415 Solid state image sensor and method for fabricating the same
06/18/2002US6407409 Nucleating gan in a reactor results in a gan nucleation layer having a thickness of a few monolayers.
06/18/2002US6407406 High operation speed and low power consumption; strained semiconductor layer applied with a tensile or compressive strain; low dislocation density and a sufficiently thin buffer layer
06/18/2002US6407405 Lamination structure of zno layers and znte layers alternately stacked on a substrate, wherein n is doped at least in the znte layer.
06/18/2002US6407398 Electron beam exposure apparatus and exposure method
06/18/2002US6407397 Charged particle beam exposure apparatus
06/18/2002US6407393 X-ray image sensor and method for fabricating the same
06/18/2002US6407386 System and method for automatic analysis of defect material on semiconductors
06/18/2002US6407385 Methods and apparatus for removing particulate foreign matter from the surface of a sample
06/18/2002US6407373 Apparatus and method for reviewing defects on an object
06/18/2002US6407368 System for maintaining a flat zone temperature profile in LP vertical furnace
06/18/2002US6407367 Heat treatment apparatus, heat treatment process employing the same, and process for producing semiconductor article
06/18/2002US6407363 Laser system and method for single press micromachining of multilayer workpieces
06/18/2002US6407360 Laser cutting apparatus and method
06/18/2002US6407359 Method of producing individual plasmas in order to create a uniform plasma for a work surface, and apparatus for producing such a plasma
06/18/2002US6407340 Electric conductor with a surface structure in the form of flanges and etched grooves
06/18/2002US6407014 Method achieving higher inversion layer mobility in novel silicon carbide semiconductor devices
06/18/2002US6407013 Soft plasma oxidizing plasma method for forming carbon doped silicon containing dielectric layer with enhanced adhesive properties
06/18/2002US6407012 Method of producing silicon oxide film, method of manufacturing semiconductor device, semiconductor device, display and infrared irradiating device
06/18/2002US6407011 Stacked dielectric film
06/18/2002US6407010 Single-substrate-heat-processing apparatus and method for semiconductor process
06/18/2002US6407009 Methods of manufacture of uniform spin-on films
06/18/2002US6407008 Method of forming an oxide layer
06/18/2002US6407007 Method to solve the delamination of a silicon nitride layer from an underlying spin on glass layer
06/18/2002US6407006 Method for integrated circuit planarization
06/18/2002US6407005 Method for forming semiconductor device to prevent electric field concentration from being generated at corner of active region
06/18/2002US6407004 Patterning connector electrode on magnetoresistive substrate
06/18/2002US6407003 Fabrication process of semiconductor device with titanium film
06/18/2002US6407002 Multilayer; barrier, dielectric, antirefelctive coating
06/18/2002US6407001 Integrated circuits
06/18/2002US6406999 Semiconductor device having reduced line width variations between tightly spaced and isolated features
06/18/2002US6406998 Forming silicon nitride overcoating
06/18/2002US6406997 Chromium films and chromium film overlayers
06/18/2002US6406996 Sub-cap and method of manufacture therefor in integrated circuit capping layers
06/18/2002US6406995 Pattern-sensitive deposition for damascene processing
06/18/2002US6406993 Method of defining small openings in dielectric layers
06/18/2002US6406992 Fabrication method for a dual damascene structure
06/18/2002US6406991 Method of manufacturing a contact element and a multi-layered wiring substrate, and wafer batch contact board
06/18/2002US6406990 Method of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrier
06/18/2002US6406989 Method of fabricating semiconductor device with bump electrodes
06/18/2002US6406988 Method of forming fine pitch interconnections employing magnetic masks
06/18/2002US6406987 Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions
06/18/2002US6406986 Fabrication of a wide metal silicide on a narrow polysilicon gate structure
06/18/2002US6406985 Method of fabricating buried contact
06/18/2002US6406984 Heating a indium, wood's metal, gallium, or alloy thereof
06/18/2002US6406983 Vapor deposition
06/18/2002US6406982 Method of improving epitaxially-filled trench by smoothing trench prior to filling
06/18/2002US6406981 Method for the manufacture of semiconductor devices and circuits
06/18/2002US6406980 Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets
06/18/2002US6406979 Method for sectioning a substrate wafer into a plurality of substrate chips
06/18/2002US6406978 Using high density hydrogen plasma
06/18/2002US6406977 Isolation region forming methods
06/18/2002US6406976 Semiconductor device and process for forming the same
06/18/2002US6406975 Method for fabricating an air gap shallow trench isolation (STI) structure
06/18/2002US6406974 Method of forming triple N well utilizing phosphorus and boron ion implantations
06/18/2002US6406973 Forming separation layer
06/18/2002US6406972 Integrated circuit, components thereof and manufacturing method
06/18/2002US6406971 Fabrication method for an embedded dynamic random access memory (DRAM)
06/18/2002US6406970 Buried strap formation without TTO deposition
06/18/2002US6406969 Method of manufacturing a thin film transistor array substrate
06/18/2002US6406968 Method of forming dynamic random access memory
06/18/2002US6406967 Method for manufacturing cylindrical storage electrode of semiconductor device
06/18/2002US6406966 Uniform emitter formation using selective laser recrystallization
06/18/2002US6406965 Method of fabricating HBT devices
06/18/2002US6406964 Method of controlling junction recesses in a semiconductor device
06/18/2002US6406963 Patterned layer is applied defining area of gate structure, and dielectric layer is applied in such way that thickness of dielectric layer next to patterned layer is larger than height of patterned layer
06/18/2002US6406962 Vertical trench-formed dual-gate FET device structure and method for creation
06/18/2002US6406961 Alternating zones of dielectric and electroconductivity; uniform thickness
06/18/2002US6406960 Process for fabricating an ONO structure having a silicon-rich silicon nitride layer
06/18/2002US6406959 Method of forming FLASH memory, method of forming FLASH memory and SRAM circuitry, and etching methods
06/18/2002US6406958 Method of manufacturing nonvolatile semiconductor memory device
06/18/2002US6406957 Methods of forming field effect transistors and related field effect transistor constructions
06/18/2002US6406956 Poly resistor structure for damascene metal gate
06/18/2002US6406955 Method for manufacturing CMOS devices having transistors with mutually different punch-through voltage characteristics
06/18/2002US6406954 Method for forming out-diffusing a dopant from the doped polysilicon into the N-type and P-type doped portion
06/18/2002US6406953 Method for fabricating an integrated circuit with a transistor electrode
06/18/2002US6406952 Process for device fabrication
06/18/2002US6406951 Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology
06/18/2002US6406950 Definition of small damascene metal gates using reverse through approach
06/18/2002US6406949 Thin film transistor-liquid crystal display and manufacturing method therefor
06/18/2002US6406948 Method for forming an ESD protection network for SOI technology with the ESD device formed in an underlying silicon substrate
06/18/2002US6406947 Method of making a low leakage dynamic threshold voltage MOS (DTMOS) transistor
06/18/2002US6406946 Thin film transistor matrix device and method for fabricating the same
06/18/2002US6406945 Method for forming a transistor gate dielectric with high-K and low-K regions
06/18/2002US6406944 Method of fabricating a reinforcement of lead bonding in microelectronic packages
06/18/2002US6406942 Flip chip type semiconductor device and method for manufacturing the same
06/18/2002US6406941 Solid-state imaging device and manufacturing method thereof
06/18/2002US6406940 Method and apparatus for stacking IC devices
06/18/2002US6406939 Flip chip assembly with via interconnection
06/18/2002US6406938 Semiconductor and flip chip packages and method having a back-side connection
06/18/2002US6406937 Method for producing an electrical connection between the front and rear sides of semiconductor chips
06/18/2002US6406934 Wafer level production of chip size semiconductor packages
06/18/2002US6406933 Production method for micromechanical components
06/18/2002US6406931 Process control; forming buffer layer
06/18/2002US6406929 Structure and method for abrupt PN junction diode formed using chemical vapor deposition processing
06/18/2002US6406925 Method and apparatus for minimizing semiconductor wafer arcing during semiconductor wafer processing
06/18/2002US6406924 Endpoint detection in the fabrication of electronic devices