| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 06/25/2002 | US6410861 Low profile interconnect structure |
| 06/25/2002 | US6410860 Electronic circuit package assembly with solder interconnection sheet |
| 06/25/2002 | US6410677 Heat resistant polymer blend |
| 06/25/2002 | US6410642 Adhesive and semiconductor devices |
| 06/25/2002 | US6410494 Cleaning agent |
| 06/25/2002 | US6410463 Method for forming film with low dielectric constant on semiconductor substrate |
| 06/25/2002 | US6410462 Method of making low-K carbon doped silicon oxide |
| 06/25/2002 | US6410461 Method of depositing sion with reduced defects |
| 06/25/2002 | US6410460 Forming metal oxides, nitrides, carbides or phosphides by high temperature vacuum deposition of intermetallics on silicon carbide; electroconductivity; integrated circuits |
| 06/25/2002 | US6410459 Wafer planarization using a uniform layer of material and method and apparatus for forming uniform layer of material used in semiconductor processing |
| 06/25/2002 | US6410458 Method and system for eliminating voids in a semiconductor device |
| 06/25/2002 | US6410457 Method for improving barrier layer adhesion to HDP-FSG thin films |
| 06/25/2002 | US6410456 Method and apparatus for insitu vapor generation |
| 06/25/2002 | US6410455 Wafer processing system |
| 06/25/2002 | US6410454 Using hydrogen free radicals generated by heating hydrogen or nonmetal halides using a hot filament in the presence of a free radical catalyst; forming conductor or insulator films |
| 06/25/2002 | US6410453 Method of processing a substrate |
| 06/25/2002 | US6410452 Method of manufacturing semiconductor device |
| 06/25/2002 | US6410451 Techniques for improving etching in a plasma processing chamber |
| 06/25/2002 | US6410448 Etching a wafer in a gas apparatus having upper, lower and peripheral electrodes attached to high and low frequency power sources and magnets to control plasma gases; high density semiconductors |
| 06/25/2002 | US6410447 Process for removing photoresist material |
| 06/25/2002 | US6410446 Method for gap filling |
| 06/25/2002 | US6410444 Composition for polishing a semiconductor device and process for manufacturing a semiconductor device using the same |
| 06/25/2002 | US6410443 Method for removing semiconductor ARC using ARC CMP buffing |
| 06/25/2002 | US6410442 Metallization of semiconductor high-speed integrated circuits by chemical-mechanical polishing; an etching solution comprising a copper(alloy) etchant, water and a surfactant |
| 06/25/2002 | US6410440 Method and apparatus for a gaseous environment providing improved control of CMP process |
| 06/25/2002 | US6410439 Semiconductor polishing apparatus and method for chemical/mechanical polishing of films |
| 06/25/2002 | US6410437 Method for etching dual damascene structures in organosilicate glass |
| 06/25/2002 | US6410436 Method of cleaning porous body, and process for producing porous body, non-porous film or bonded substrate |
| 06/25/2002 | US6410435 Ultra large scale integration (ulsi); copper interconnect system containing chromium oxide |
| 06/25/2002 | US6410434 Low pressure chemical vapor deposition of silane and phosphine; reduced defects; uniform sheet resistance |
| 06/25/2002 | US6410433 Integrated circuits containing copper films |
| 06/25/2002 | US6410432 Tantalum (ta); tantalum nitride (tanx); chemical vapor deposition simultaneous nitriding and reduction to metal; integrated circuits containing copper film |
| 06/25/2002 | US6410430 Enhanced ultra-shallow junctions in CMOS using high temperature silicide process |
| 06/25/2002 | US6410429 Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions |
| 06/25/2002 | US6410428 Nitride deposition on tungsten-polycide gate to prevent abnormal tungsten silicide oxidation |
| 06/25/2002 | US6410427 Metal silicidation methods and methods for using same |
| 06/25/2002 | US6410426 Damascene cap layer process for integrated circuit interconnects |
| 06/25/2002 | US6410425 Integrated circuit with stop layer and method of manufacturing the same |
| 06/25/2002 | US6410424 Process flow to optimize profile of ultra small size photo resist free contact |
| 06/25/2002 | US6410423 Semiconductor device and manufacturing method thereof |
| 06/25/2002 | US6410422 Method of forming a local interconnect contact opening |
| 06/25/2002 | US6410421 Semiconductor device with anti-reflective structure and methods of manufacture |
| 06/25/2002 | US6410420 Method of fabricating silicide pattern structures |
| 06/25/2002 | US6410419 Silicon carbide barrier layers for porous low dielectric constant materials |
| 06/25/2002 | US6410418 Recess metallization via selective insulator formation on nucleation/seed layer |
| 06/25/2002 | US6410417 Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymer |
| 06/25/2002 | US6410415 Flip chip mounting technique |
| 06/25/2002 | US6410414 Method for fabricating a semiconductor device |
| 06/25/2002 | US6410413 Semiconductor device with transparent link area for silicide applications and fabrication thereof |
| 06/25/2002 | US6410412 Methods for fabricating memory devices |
| 06/25/2002 | US6410411 Sputtering chromium nitride thin film as electrode of circuit elements; thin film transistors |
| 06/25/2002 | US6410410 Method of forming lightly doped regions in a semiconductor device |
| 06/25/2002 | US6410409 Implanted barrier layer for retarding upward diffusion of substrate dopant |
| 06/25/2002 | US6410408 CVD film formation method |
| 06/25/2002 | US6410407 Product including a silicon-containing functional layer and an insulating layer made of silicon dioxide, and method fabricating the product |
| 06/25/2002 | US6410406 Semiconductor device including edge bond pads and methods |
| 06/25/2002 | US6410405 Method for forming a field oxide film on a semiconductor device including mask spacer and rounding edge |
| 06/25/2002 | US6410404 Process for manufacturing SOI integrated circuits and circuits made thereby |
| 06/25/2002 | US6410403 Method for planarizing a shallow trench isolation |
| 06/25/2002 | US6410402 Method of providing variant fills in semiconductor trenches |
| 06/25/2002 | US6410400 Method of manufacturing Ta2O5capacitor using Ta2O5thin film as dielectric layer |
| 06/25/2002 | US6410399 Process to lower strap, wordline and bitline contact resistance in trench-based DRAMS by silicidization |
| 06/25/2002 | US6410398 Device for the adjustment of circuits after packaging, corresponding fabrication process and induction device |
| 06/25/2002 | US6410397 Method for manufacturing a dielectric trench capacitor with a stacked-layer structure |
| 06/25/2002 | US6410395 Epitaxial deposition of two monocrystalline silicon layers and silicon germanium middle layer; forming base zone; doping at later stage; npn and pnp transistors |
| 06/25/2002 | US6410394 Method for forming self-aligned channel implants using a gate poly reverse mask |
| 06/25/2002 | US6410393 Semiconductor device with asymmetric channel dopant profile |
| 06/25/2002 | US6410392 Method of producing MOS transistor |
| 06/25/2002 | US6410391 Method for producing an EEPROM memory cell with a trench capacitor |
| 06/25/2002 | US6410390 Nonvolatile memory device and method for fabricating the same |
| 06/25/2002 | US6410389 Non-volatile memory cell with a single level of polysilicon, in particular of the flash EEPROM type, and method for manufacturing the same |
| 06/25/2002 | US6410388 Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device |
| 06/25/2002 | US6410387 Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry |
| 06/25/2002 | US6410386 Method for forming a metal capacitor in a damascene process |
| 06/25/2002 | US6410385 ROM-embedded-DRAM |
| 06/25/2002 | US6410384 Forming doped dielectric layer along a surface of a trench, ion-implanted-sensitive resist is formed over the doped dielectric layer, implanting, removing vertical surface, thermal treatment to diffuse the dopants |
| 06/25/2002 | US6410383 Method of forming conducting diffusion barriers |
| 06/25/2002 | US6410382 Fabrication method of semiconductor device |
| 06/25/2002 | US6410381 Ru film is deposited by lpcvd, and re-deposited in situ by pecvd amorphous taon film on the lower electrode crystalled using thermal treatment; upper electrode on the crystallized taon film. |
| 06/25/2002 | US6410380 Method for making semiconductor device incorporating and electrical contact to an internal conductive layer |
| 06/25/2002 | US6410379 Method of forming a submerged semiconductor structure |
| 06/25/2002 | US6410378 Method of fabrication of semiconductor structures by ion implantation |
| 06/25/2002 | US6410377 Method for integrating CMOS sensor and high voltage device |
| 06/25/2002 | US6410376 Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration |
| 06/25/2002 | US6410375 Methods of forming transistors including gate dielectric layers having different nitrogen concentrations |
| 06/25/2002 | US6410374 Illuminating high-speed ions to implant impurities; laser or lamp annealing |
| 06/25/2002 | US6410373 Method of forming polysilicon thin film transistor structure |
| 06/25/2002 | US6410372 Manufacture of thin film transistors |
| 06/25/2002 | US6410371 Wafer bonding and removal of undesired portion of substrate to form an upper silicon layer; increased electron mobility |
| 06/25/2002 | US6410368 Method of manufacturing a semiconductor device with TFT |
| 06/25/2002 | US6410366 Semiconductor device and manufacturing method thereof, circuit board and electronic equipment |
| 06/25/2002 | US6410365 Semiconductor device with two stacked chips in one resin body and method of producing |
| 06/25/2002 | US6410364 Semiconductor device, method of connecting a semiconductor chip, circuit board, and electronic equipment |
| 06/25/2002 | US6410359 Reduced leakage trench isolation |
| 06/25/2002 | US6410357 Structure of critical dimension bar |
| 06/25/2002 | US6410356 Silicon carbide large area device fabrication apparatus and method |
| 06/25/2002 | US6410355 Semiconductor package using terminals formed on a conductive layer of a circuit board |
| 06/25/2002 | US6410354 Semiconductor substrate test device and method |
| 06/25/2002 | US6410353 Contact chain for testing and its relevantly debugging method |
| 06/25/2002 | US6410351 Method and apparatus for modeling thickness profiles and controlling subsequent etch process |