| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/09/2002 | US6418187 X-ray mask structure, and X-ray exposure method and apparatus using the same |
| 07/09/2002 | US6418074 Semiconductor memory device having driver circuit which supplies temporary accelerated charge |
| 07/09/2002 | US6418072 Semiconductor integrated circuit |
| 07/09/2002 | US6418067 Semiconductor memory device suitable for merging with logic |
| 07/09/2002 | US6418058 Nonvolatile semiconductor memory device |
| 07/09/2002 | US6418049 Programmable sub-surface aggregating metallization structure and method of making same |
| 07/09/2002 | US6418046 MRAM architecture and system |
| 07/09/2002 | US6418030 Multi-chip module |
| 07/09/2002 | US6418008 Enhanced capacitor shape |
| 07/09/2002 | US6417974 Objective, in particular an objective for a semiconductor lithography projection exposure machine, and a production method |
| 07/09/2002 | US6417967 System and method for efficient illumination in color projection displays |
| 07/09/2002 | US6417927 Method and apparatus for accurately compensating both long and short term fluctuations in the refractive index of air in an interferometer |
| 07/09/2002 | US6417922 Alignment device and lithographic apparatus comprising such a device |
| 07/09/2002 | US6417914 Stage device and exposure apparatus |
| 07/09/2002 | US6417896 Active matrix display device |
| 07/09/2002 | US6417754 Three-dimensional coil inductor |
| 07/09/2002 | US6417726 Semiconductor device capable of adjusting an internal power supply potential in a wide range |
| 07/09/2002 | US6417722 Sense amplifier configuration having a field-effect transistor having a short channel length and an adjustable threshold voltage |
| 07/09/2002 | US6417718 Semiconductor device without limitation on insert orientation on board |
| 07/09/2002 | US6417695 Antifuse reroute of dies |
| 07/09/2002 | US6417684 Securement of test points in a test head |
| 07/09/2002 | US6417683 Apparatus for electrical testing of a substrate having a plurality of terminals |
| 07/09/2002 | US6417677 Antistatic conductive pin mounting apparatus for a photomask |
| 07/09/2002 | US6417673 Scanning depletion microscopy for carrier profiling |
| 07/09/2002 | US6417626 Immersed inductively—coupled plasma source |
| 07/09/2002 | US6417581 Circuit for automatically inverting electrical lines connected to a device upon detection of a miswired condition to allow for operation of device even if miswired |
| 07/09/2002 | US6417575 Semiconductor device and fabrication process therefor |
| 07/09/2002 | US6417574 Surface-acoustic-wave device for flip-chip mounting |
| 07/09/2002 | US6417572 Process for producing metal interconnections and product produced thereby |
| 07/09/2002 | US6417571 Single grain copper interconnect with bamboo structure in a trench |
| 07/09/2002 | US6417570 Layered dielectric film structure suitable for gate dielectric application in sub-0.25 μm technologies |
| 07/09/2002 | US6417569 Tungsten barrier; integrated circuits |
| 07/09/2002 | US6417568 Semiconductor device |
| 07/09/2002 | US6417567 Multilayer, silicon, metal silicide, titanium oxynitride |
| 07/09/2002 | US6417566 Void eliminating seed layer and conductor core integrated circuit interconnects |
| 07/09/2002 | US6417565 Multilayer; semiconductor overcoated with dielectrics |
| 07/09/2002 | US6417564 Semiconductor element with metal layer |
| 07/09/2002 | US6417562 Silicon verification with embedded testbenches |
| 07/09/2002 | US6417561 Keepers for MRAM electrodes |
| 07/09/2002 | US6417559 Semiconductor wafer assemblies comprising photoresist over silicon nitride materials |
| 07/09/2002 | US6417558 Semiconductor device having a reduced parasitic capacitance bonding pad structure |
| 07/09/2002 | US6417557 Semiconductor device having a capacitance adjustment section |
| 07/09/2002 | US6417556 High K dielectric de-coupling capacitor embedded in backend interconnect |
| 07/09/2002 | US6417555 Semiconductor device and manufacturing method therefor |
| 07/09/2002 | US6417551 Semiconductor device and method of manufacturing the same |
| 07/09/2002 | US6417550 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage |
| 07/09/2002 | US6417549 Static random access memory device and method for manufacturing the same |
| 07/09/2002 | US6417548 Variable work function transistor high density mask ROM |
| 07/09/2002 | US6417547 Semiconductor device with a halo structure |
| 07/09/2002 | US6417546 P-type FET in a CMOS with nitrogen atoms in the gate dielectric |
| 07/09/2002 | US6417545 Semiconductor device |
| 07/09/2002 | US6417543 MIS semiconductor device with sloped gate, source, and drain regions |
| 07/09/2002 | US6417540 Non-volatile semiconductor memory device and method for manufacturing the same |
| 07/09/2002 | US6417539 High density memory cell assembly and methods |
| 07/09/2002 | US6417538 Nonvolative semiconductor memory device with high impurity concentration under field oxide layer |
| 07/09/2002 | US6417537 Multilayer containing oxynitride |
| 07/09/2002 | US6417536 Semiconductor device with memory capacitor having an electrode of Si1-x Gex |
| 07/09/2002 | US6417535 Vertical interdigitated metal-insulator-metal capacitor for an integrated circuit |
| 07/09/2002 | US6417534 Semiconductor device and method of fabricating the same |
| 07/09/2002 | US6417533 Semiconductor device having capacitor which assures sufficient capacity without requiring large space and method of producing the same |
| 07/09/2002 | US6417530 Sense amplifier layout method, and semiconductor memory device using the same |
| 07/09/2002 | US6417529 Function cell, semiconductor device including function cell, and semiconductor circuit designing method using function cell |
| 07/09/2002 | US6417521 Transmission circuit and semiconductor device |
| 07/09/2002 | US6417519 Group 3,4 and 4 intermetallics |
| 07/09/2002 | US6417516 Electron beam lithographing method and apparatus thereof |
| 07/09/2002 | US6417515 In-situ ion implant activation and measurement apparatus |
| 07/09/2002 | US6417484 Laser marking system for dice carried in trays and method of operation |
| 07/09/2002 | US6417442 Solar battery assembly and method of forming a solar battery assembly |
| 07/09/2002 | US6417317 Condensation polymerization of trifunctional phenolic compound with ortho- and para-positioned hydrogens in presence of aldehyde or ketone; positive photoresists, coatings; heat resistance |
| 07/09/2002 | US6417147 Cleaning agent composition, method for cleaning and use thereof |
| 07/09/2002 | US6417118 Ultraviolet radiation and siloxane solutions, rinsing, purging with nitrogen |
| 07/09/2002 | US6417116 Semiconductor device having a multilayer interconnection structure |
| 07/09/2002 | US6417115 Treatment of dielectric materials |
| 07/09/2002 | US6417114 Method for fabricating semiconductor integrated circuit device |
| 07/09/2002 | US6417113 Multilayer structure with electroconductive layer, silicide layer, silicon nitride layer, patterns of germanium silicon alloy and removal |
| 07/09/2002 | US6417112 Removal of etch residues from integrated circuits with dielectric and copper material with water or solvents |
| 07/09/2002 | US6417111 Plasma processing apparatus |
| 07/09/2002 | US6417110 Method for constructing heat resistant electrode structures on silicon substrates |
| 07/09/2002 | US6417109 Chemical-mechanical etch (CME) method for patterned etching of a substrate surface |
| 07/09/2002 | US6417108 Semiconductor substrate and method of manufacturing the same |
| 07/09/2002 | US6417107 Method for manufacturing a functional device by forming 45-degree-surface on (100) silicon |
| 07/09/2002 | US6417106 Underlayer liner for copper damascene in low k dielectric |
| 07/09/2002 | US6417105 Produced by reactive sintering and vacuum hot pressing powders and products such as sputtering targets |
| 07/09/2002 | US6417104 Forming conductive line for semiconductors, removal of stacks then annealing cobalt, followed by a silicon layer and a top insulator layer. the blanket stack is patterned |
| 07/09/2002 | US6417102 Semiconductor processing method using high pressure liquid media treatment |
| 07/09/2002 | US6417101 Method for manufacturing semiconductor memory device incorporating therein copacitor |
| 07/09/2002 | US6417100 Forming integrated circuits and dielectrics layers, forming apertures in dielectric layers, depositing barriers and conductors then annealing |
| 07/09/2002 | US6417099 Method for controlling dopant diffusion in a plug-shaped doped polysilicon layer on a semiconductor wafer |
| 07/09/2002 | US6417098 Forming metal connectors on substrates, deposits of damascene |
| 07/09/2002 | US6417097 Methods of forming a contact structure in a semiconductor device |
| 07/09/2002 | US6417096 Method for avoiding photo residue in dual damascene with acid treatment |
| 07/09/2002 | US6417095 Method for fabricating a dual damascene structure |
| 07/09/2002 | US6417094 Dual-damascene interconnect structures and methods of fabricating same |
| 07/09/2002 | US6417093 Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing |
| 07/09/2002 | US6417092 Integrated circuits with insulating material |
| 07/09/2002 | US6417091 Mask has pattern of rectangular shapes arranged longitudinally in rows spaced evenly apart and offset from the rectangular shapes in neighboring rows to define t-shapes connected to and offset from each other; simplification |
| 07/09/2002 | US6417090 Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer |
| 07/09/2002 | US6417089 Method of forming solder bumps with reduced undercutting of under bump metallurgy (UBM) |
| 07/09/2002 | US6417088 Method of application of displacement reaction to form a conductive cap layer for flip-chip, COB, and micro metal bonding |
| 07/09/2002 | US6417087 Forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface |