| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 07/16/2002 | US6420745 Nonvolatile ferroelectric memory and its manufacturing method |
| 07/16/2002 | US6420744 Ferroelectric capacitor and method for fabricating ferroelectric capacitor |
| 07/16/2002 | US6420742 Ferroelectric memory transistor with high-k gate insulator and method of fabrication |
| 07/16/2002 | US6420741 Ferroelectric memory having electromagnetic wave shield structure |
| 07/16/2002 | US6420740 Lead germanate ferroelectric structure with multi-layered electrode |
| 07/16/2002 | US6420739 GaAs semiconductor device having a capacitor |
| 07/16/2002 | US6420738 Electric charge detector |
| 07/16/2002 | US6420730 Elevated transistor fabrication technique |
| 07/16/2002 | US6420729 Process to produce ultrathin crystalline silicon nitride on Si (111) for advanced gate dielectrics |
| 07/16/2002 | US6420725 Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
| 07/16/2002 | US6420722 Method for sample separation and lift-out with one cut |
| 07/16/2002 | US6420717 Method and apparatus for real-time correction of resist heating in lithography |
| 07/16/2002 | US6420716 Servo control method and its application in a lithographic apparatus |
| 07/16/2002 | US6420714 Electron beam imaging apparatus |
| 07/16/2002 | US6420713 Image position and lens field control in electron beam systems |
| 07/16/2002 | US6420678 Method for separating non-metallic substrates |
| 07/16/2002 | US6420664 Metal foil having bumps, circuit substrate having the metal foil, and semiconductor device having the circuit substrate |
| 07/16/2002 | US6420661 Connector element for connecting microelectronic elements |
| 07/16/2002 | US6420651 Integrated circuit package with bond wires at the corners of an integrated circuit |
| 07/16/2002 | US6420643 Silicon thin-film, integrated solar cell, module, and methods of manufacturing the same |
| 07/16/2002 | US6420441 Dispersing removable crosslinked polymer porogens in a polysiloxane, curing, and heating to remove porogen; low dielectric constant; high porosity; insulation materials |
| 07/16/2002 | US6420283 Crystallization of nitrides layers on synthetic mica substrates |
| 07/16/2002 | US6420282 Construction of thin film transistors used as liquid crystal displays on glass substrates; vapor deposition; sputtering |
| 07/16/2002 | US6420281 High-temperature heat treatment of the oxidized film to drive out contamination acquired from the doped layer beneath to improve the quality of the oxidized film such as durability against a high voltage |
| 07/16/2002 | US6420280 Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer |
| 07/16/2002 | US6420279 Coating thin films of hafnium and zirconium oxide on silicon semiconductors, by purging a chamber of hafnium and zirconium nitrate with nitrogen, then hydrating with water vapor |
| 07/16/2002 | US6420278 Method for improving the dielectric constant of silicon-based semiconductor materials |
| 07/16/2002 | US6420277 Process for inhibiting crack formation in low dielectric constant dielectric films of integrated circuit structure |
| 07/16/2002 | US6420276 Semiconductor device and semiconductor device manufacturing method |
| 07/16/2002 | US6420273 Self-aligned etch-stop layer formation for semiconductor devices |
| 07/16/2002 | US6420272 Method for removal of hard mask used to define noble metal electrode |
| 07/16/2002 | US6420271 Method of forming a pattern |
| 07/16/2002 | US6420270 Method of producing an etch pattern |
| 07/16/2002 | US6420268 Methods of forming materials within openings, and methods of forming isolation regions |
| 07/16/2002 | US6420267 Method for forming an integrated barrier/plug for a stacked capacitor |
| 07/16/2002 | US6420266 Methods for creating elements of predetermined shape and apparatuses using these elements |
| 07/16/2002 | US6420265 Method for polishing semiconductor device |
| 07/16/2002 | US6420264 Method of forming a silicide region in a Si substrate and a device having same |
| 07/16/2002 | US6420263 Method for controlling extrusions in aluminum metal lines and the device formed therefrom |
| 07/16/2002 | US6420262 Coating insulator and conductor barrier layers on semiconductors to prevent migration, electrical resistance and capacitance; vapor deposition |
| 07/16/2002 | US6420261 Semiconductor device manufacturing method |
| 07/16/2002 | US6420260 Ti/Tinx underlayer which enables a highly <111> oriented aluminum interconnect |
| 07/16/2002 | US6420259 Formation of a self-aligned structure |
| 07/16/2002 | US6420258 Selective growth of copper for advanced metallization |
| 07/16/2002 | US6420257 Process for forming trenches and contacts during the formation of a semiconductor memory device |
| 07/16/2002 | US6420256 Method of improving interconnect of semiconductor devices by using a flattened ball bond |
| 07/16/2002 | US6420255 Mounting substrate with a solder resist layer and method of forming the same |
| 07/16/2002 | US6420253 Thiol or sulfur portion of an alkyl mercaptan or a disulfide derivative bonds with a noble metal, alkyl portion is oriented away from the surface |
| 07/16/2002 | US6420252 Methods of forming robust metal contacts on compound semiconductors |
| 07/16/2002 | US6420251 Coating conductor layers on dielectrics, etching patterns, appyling silicon oxide and a polyarylcyclobutene, then etching to form surface flatness; semiconductors |
| 07/16/2002 | US6420250 Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates |
| 07/16/2002 | US6420249 Method for fabricating a floating gate semiconductor device |
| 07/16/2002 | US6420248 Double gate oxide layer method of manufacture |
| 07/16/2002 | US6420247 Method of forming structures on a semiconductor including doping profiles using thickness of photoresist |
| 07/16/2002 | US6420246 Optical laser annealing to remove metal catalyst element; uniform rapid thermal annealing; thin film transistor |
| 07/16/2002 | US6420245 Method for singulating semiconductor wafers |
| 07/16/2002 | US6420244 Method of making wafer level chip scale package |
| 07/16/2002 | US6420243 Method for producing SOI wafers by delamination |
| 07/16/2002 | US6420242 Separation of thin films from transparent substrates by selective optical processing |
| 07/16/2002 | US6420241 Method for forming an isolation region in a semiconductor device and resulting structure using a two step oxidation process |
| 07/16/2002 | US6420240 Method for reducing the step height of shallow trench isolation structures |
| 07/16/2002 | US6420239 Memory cell with trench capacitor and method of fabricating the memory cell |
| 07/16/2002 | US6420238 Method of fabricating high-capacitance capacitive elements in a semiconductor substrate |
| 07/16/2002 | US6420237 Method of manufacturing twin bit cell flash memory device |
| 07/16/2002 | US6420236 Lower gate workfunction and, as a result, a lower threshold voltage; hydrogen reduction of metal gates immediately after metal deposition |
| 07/16/2002 | US6420235 Method of forming self-aligned mask ROM |
| 07/16/2002 | US6420234 Short channel length transistor and method of fabricating the same |
| 07/16/2002 | US6420233 Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate electrode dopant profile |
| 07/16/2002 | US6420232 Very high density, high speed and low power; spacer formation technique without the conventional lithographic limitation; overall channel length can be smaller and is mainly determined by the composite widths of the polycrystalline silicon spacers |
| 07/16/2002 | US6420231 Processing techniques for making a dual floating gate EEPROM cell array |
| 07/16/2002 | US6420230 Capacitor fabrication methods and capacitor constructions |
| 07/16/2002 | US6420229 Method for fabricating a cylindrical capacitor in which a storage electrode is formed on both the upper and side surfaces of a conductor plug |
| 07/16/2002 | US6420228 Method for the production of a DRAM cell configuration |
| 07/16/2002 | US6420227 Semiconductor integrated circuit device and process for manufacture of the same |
| 07/16/2002 | US6420226 Method of defining a buried stack capacitor structure for a one transistor RAM cell |
| 07/16/2002 | US6420225 Method of fabricating power rectifier device |
| 07/16/2002 | US6420224 Stepper alignment mark formation with dual field oxide process |
| 07/16/2002 | US6420223 Manufacturing process for non-volatile floating gate memory cells integrated on a semiconductor substrate and comprised in a cell matrix with an associated control circuitry |
| 07/16/2002 | US6420222 Method of producing semiconductor having two-layer polycrystalline silicon structure |
| 07/16/2002 | US6420221 Method of manufacturing a highly latchup-immune CMOS I/O structure |
| 07/16/2002 | US6420220 Method of forming electrode for high performance semiconductor devices |
| 07/16/2002 | US6420219 Thin film transistors and method of forming thin film transistors |
| 07/16/2002 | US6420218 Ultra-thin-body SOI MOS transistors having recessed source and drain regions |
| 07/16/2002 | US6420216 Fuse processing using dielectric planarization pillars |
| 07/16/2002 | US6420215 Three-dimensional memory array and method of fabrication |
| 07/16/2002 | US6420214 Polycyanurates |
| 07/16/2002 | US6420213 Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive |
| 07/16/2002 | US6420212 Method and apparatus to enclose dice |
| 07/16/2002 | US6420211 Method for protecting an integrated circuit chip |
| 07/16/2002 | US6420210 Semiconductor device and method for manufacturing the same |
| 07/16/2002 | US6420209 Integrated circuits and methods for their fabrication |
| 07/16/2002 | US6420208 Method of forming an alternative ground contact for a semiconductor die |
| 07/16/2002 | US6420207 Full body gold; improved electrical and mechanical connects; copper circuit on wire bond side is fully covered, solder mask applied directly to semiconductor to avoid contact with gold; ball area protected by metall or an organic solderable |
| 07/16/2002 | US6420206 Optical membrane singulation process utilizing backside and frontside protective coating during die saw |
| 07/16/2002 | US6420201 Method for forming a bond wire pressure sensor die package |
| 07/16/2002 | US6420200 Method of manufacturing an electro-optical device |
| 07/16/2002 | US6420197 Improved crystalline characteristics of algain nitride; strain reducing layer between layers of different thermal expansion coefficients; blue laser |
| 07/16/2002 | US6420194 Method for extracting process determinant conditions from a plurality of process signals |
| 07/16/2002 | US6420193 Repair of film having an SI-O backbone |
| 07/16/2002 | US6420192 Method of manufacturing semiconductor memory |