Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2002
07/18/2002US20020094660 Spacer elements for interactive information devices and method for making same
07/18/2002US20020094659 Method for forming isolation layer of semiconductor device
07/18/2002US20020094658 Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter EPI layer
07/18/2002US20020094657 Method for forming a capacitor in a semiconductor device
07/18/2002US20020094656 Metal-insulator-metal capacitor in copper
07/18/2002US20020094654 Aluminum gallium nitride layer; preventing crack generation; light emitting and laser diodes
07/18/2002US20020094653 Trench capacitors in soi substrstes
07/18/2002US20020094652 Graded layer for use in semiconductor circuits and method for making same
07/18/2002US20020094651 Low dielectric constant STI with SOI devices
07/18/2002US20020094650 Field effect transistor and method of fabrication
07/18/2002US20020094649 Shallow trench isolation using non-conformal dielectric material and planarizatrion
07/18/2002US20020094648 Extended poly buffer STI scheme
07/18/2002US20020094647 Method of manufacturing a semiconductor device
07/18/2002US20020094646 Method for fabricating embedded nonvolatile semiconductor memory cells
07/18/2002US20020094645 Process for making mask ROM using a salicide process and mask ROM
07/18/2002US20020094644 Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids
07/18/2002US20020094643 Mos device having a passivated semiconductor-dielectric interface
07/18/2002US20020094642 Semiconductor device and method of manufacturing the same
07/18/2002US20020094641 Method for fabricating floating gate
07/18/2002US20020094640 P-channel dynamic flash memory cells with ultrathin tunnel oxides
07/18/2002US20020094639 Inexpensive, reliable, planar RFID tag structure and method for making same
07/18/2002US20020094638 Method for manufacturing nonvolatile semiconductor memory with narrow variation in threshold voltages of memory cells
07/18/2002US20020094637 Dual mask process for semiconductor devices
07/18/2002US20020094636 Method and structure for an improved floating gate memory cell
07/18/2002US20020094635 Method for fabricating a trench MOS power transistor
07/18/2002US20020094634 Methods of forming an integrated circuit capacitor in which a metal preprocessed layer is formed on an electrode thereof
07/18/2002US20020094633 Semiconductor device and method of manufacturing the same
07/18/2002US20020094632 Capacitor fabrication methods and capacitor constructions
07/18/2002US20020094631 Method of forming semiconductor device having contact pad on source/drain region in peripheral circuit area
07/18/2002US20020094629 SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit
07/18/2002US20020094628 Integrated circuit having at least two vertical MOS transistors and method for manufacturing same
07/18/2002US20020094625 Dry etching with reduced damage to MOS device
07/18/2002US20020094624 Self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a
07/18/2002US20020094622 Process flow for a performance enhanced MOSFET with self-aligned, recessed channel
07/18/2002US20020094621 Methods of forming a nitrogen enriched region
07/18/2002US20020094620 Transistor Structures
07/18/2002US20020094619 6F2 Trench edram cell with double-gated vertical MOSFET and self-aligned STI
07/18/2002US20020094618 Field effect transistor and method of fabrication
07/18/2002US20020094617 Capacitance elements and method of manufacturing the same
07/18/2002US20020094616 Four transistors static-random-access-memory and forming method
07/18/2002US20020094615 Semiconductor device and method for manufacturing the same
07/18/2002US20020094614 Method of manufacturing a semiconductor device having reduced power consumption without a reduction in the source/drain breakdown voltage
07/18/2002US20020094613 Method of manufacturing semiconductor device
07/18/2002US20020094612 Method of manufacturing semiconductor device
07/18/2002US20020094610 Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device
07/18/2002US20020094607 Electronic component with stacked semiconductor chips and method of producing the component
07/18/2002US20020094606 Fabrication process of semiconductor package and semiconductor package
07/18/2002US20020094605 Method for fabricating a stacked chip package
07/18/2002US20020094604 Method for fabricating a multilayer ceramic substrate
07/18/2002US20020094600 Substrate processing apparatus and method for manufacturing a semiconductor device employing same
07/18/2002US20020094595 Method for making flash memory with UV opaque passivation layer
07/18/2002US20020094593 Method for adjusting optical properties of an anti-reflective coating layer
07/18/2002US20020094591 Apparatus and method for monitoring substrate biasing during plasma processing of a substrate
07/18/2002US20020094587 Method for forming capacitor having lower electrode formed by iridium/platinum layer
07/18/2002US20020094502 Substrate processing apparatus and method for manufacturing semiconductor device
07/18/2002US20020094496 Applying in a predetermined pattern an activating light curable liquid to a portion of a substrate, surface area of the substrate is less than that of the template
07/18/2002US20020094493 Method of forming partial reverse active mask
07/18/2002US20020094489 Photolithography for fine patterned resist layer having orthogonal cross-section profile with high photosensitivity and pattern resolution by exposure to excimer laser; for manufacture of semiconductors
07/18/2002US20020094483 Pattern is transferred to photoresist on semiconductor wafer via reduction projection exposure to variety of waverlengths using photomask; photolithography
07/18/2002US20020094442 Conductive layer, an anti-reflection coating (ARC) thereon, a blocking layer located on the ARC, and an oxygen-containing anti-reflection enforcing layer (silicon oxynitride) located the blocking layer
07/18/2002US20020094425 Process for depositing a tungsten-based and/or molybdenum-based layer on a rigid substrate, and substrate thus coated
07/18/2002US20020094388 Low temperature, high quality silicon dioxide thin films deposited using tetramethylsilane (TMS) for stress control and coverage applications
07/18/2002US20020094378 Carbonitride coated component of semiconductor processing equipment and method of manufacturing thereof
07/18/2002US20020094374 A magentic layer is formed over the substrate, which has a first value, ion implanting a portion of magnetic layer, ion implanted magnetic layer has a second value of magnetic characteristics different from first value
07/18/2002US20020094306 Gas recirculating system is blown into the sealed vacuum chamber so gas flow is in a predetermined direction along the processing portion; for semiconductor manufacture (X-ray exposure)
07/18/2002US20020094265 Substrate conveyer robot
07/18/2002US20020094260 Apparatus and methods for manipulating semiconductor wafers
07/18/2002US20020094256 Stocker apparatus with increased input/output capacity
07/18/2002US20020094120 Method and system for inspecting a pattern
07/18/2002US20020094063 Laser plasma EUV light source apparatus and target used therefor
07/18/2002US20020094008 Laser annealing method and semiconductor device fabricating method
07/18/2002US20020093997 Laser processing
07/18/2002US20020093867 Semiconductor device having electric fuse element
07/18/2002US20020093858 Non-volatile semiconductor memory cell having a metal oxide dielectric, and method for fabricating the memory cell
07/18/2002US20020093851 Semiconductor memory and its usage
07/18/2002US20020093849 Thin film magnetic memory device capable of easily controlling a data write current
07/18/2002US20020093848 Device for evaluating cell resistances in a magnetoresistive memory
07/18/2002US20020093846 Nonvolatile ferroelectric memory device and method for detecting weak cell using the same
07/18/2002US20020093845 Magnetic semiconductor memory apparatus and method of manufacturing the same
07/18/2002US20020093843 Semiconductor integrated circuit device
07/18/2002US20020093812 Method and apparatus for illuminating projecting features on the surface of a semiconductor wafer
07/18/2002US20020093802 High-g mounting arrangement for electronic chip carrier
07/18/2002US20020093781 Capacitor for semiconductor configuration and method for fabricating a dielectric layer therefor
07/18/2002US20020093780 Highly efficient capacitor structures with enhanced matching properties
07/18/2002US20020093740 System and method for efficient illumination in color projection displays
07/18/2002US20020093648 Methods and systems for determining an implant characterstic and a presence of defects on a specimen
07/18/2002US20020093636 Illumination system and exposure apparatus and method
07/18/2002US20020093635 Position detection apparatus having a plurality of detection sections, and exposure apparatus
07/18/2002US20020093600 Array substrate for a liquid crystal display device and method of manufacturing the same
07/18/2002US20020093581 X-ray imaging device
07/18/2002US20020093414 Patterned ground shield for mirror current elimination
07/18/2002US20020093361 Engagement probes
07/18/2002US20020093360 Integrate circuit device
07/18/2002US20020093358 Parallel logic device/circuit tester for testing plural logic devices/circuits and parallel memory chip repairing apparatus
07/18/2002US20020093353 Wafer probe station having environment control enclosure
07/18/2002US20020093350 Semiconductor device test method and semiconductor device tester
07/18/2002US20020093130 Die bonder and/or wire bonder with a suction device for pulling flat and holding down a curved substrate
07/18/2002US20020093122 camouflaging surface treatments having reduced visibility to vision enhancing devices, and surfaces providing reduced muffling
07/18/2002US20020093120 Manufacturing method of an electronic device package
07/18/2002US20020093112 Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask