Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2002
09/19/2002US20020132442 Method for fabricating a metal resistor in an IC chip and related structure
09/19/2002US20020132441 Suppression of cross diffusion and gate depletion
09/19/2002US20020132440 Process for producing two differently doped adjacent regions in an integrated semiconductor
09/19/2002US20020132439 Integrated circuit components thereof and manufacturing method
09/19/2002US20020132438 Epitaxial base bipolar transistor with raised extrinsic base
09/19/2002US20020132437 Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch
09/19/2002US20020132436 EEPROM array and method for operation thereof
09/19/2002US20020132435 High performance bipolar transistor
09/19/2002US20020132434 Stepped collector implant and method for fabrication
09/19/2002US20020132433 Method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide
09/19/2002US20020132432 Field effect transistor having dielectrically isolated sources and drains and method for making same
09/19/2002US20020132431 Method for forming notch gate having self-aligned raised source/drain structure
09/19/2002US20020132430 Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array
09/19/2002US20020132429 Method for fabricating a mos transistor of an embedded memory
09/19/2002US20020132428 Method for fabricating a MOS transistor of an embedded memory
09/19/2002US20020132427 Modified source/drain re-oxidation method and system
09/19/2002US20020132426 Semiconductor memory and process for fabricating the same
09/19/2002US20020132425 Method for fabricating NOR type flash memory device
09/19/2002US20020132424 Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same
09/19/2002US20020132423 Method of forming a uniform collar oxide layer over an upper portion of a sidewall of a trench extending into a semiconductor substrate
09/19/2002US20020132422 Method of deep trench formation with improved profile control and surface area
09/19/2002US20020132421 Method for manufacturing a trench capacitor of a memory cell of a semiconductor memory
09/19/2002US20020132420 Process for producing a first electrode and a second electrode, electronic component and electronic memory element
09/19/2002US20020132419 Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry
09/19/2002US20020132416 Semiconductor device and method of manufacturing the same
09/19/2002US20020132415 Metal gate stack with etch stop layer having implanted metal species
09/19/2002US20020132414 Method for forming memory cell by using a dummy polysilicon layer
09/19/2002US20020132413 Method of fabricating a MOS transistor
09/19/2002US20020132412 Method to fabricate surface p-channel CMOS
09/19/2002US20020132411 Semiconducting devices and method of making thereof
09/19/2002US20020132410 Nonvolatile memory device and method for fabricating the same
09/19/2002US20020132409 Substrate processing apparatus
09/19/2002US20020132408 Asymmetric organocyclosiloxanes and their use for making organosilicon polymer low-k dielectric film
09/19/2002US20020132407 Ultra-shallow junction formation for deep sub-micron complementary metal-oxide-semiconductor
09/19/2002US20020132406 High-voltage transistor with JFET conduction channels
09/19/2002US20020132405 Method of fabricating a high-voltage transistor
09/19/2002US20020132404 MOS transistor with two empty side slots on its gate and its method of formation
09/19/2002US20020132403 Method of fabricating a self-align contact with a disposable spacer
09/19/2002US20020132402 Method of manufacturing a semiconductor device
09/19/2002US20020132401 Method of manufacturing a transistor
09/19/2002US20020132400 Novel design and process for a dual gate structure
09/19/2002US20020132399 Semiconductor device and method of manufacturing thereof
09/19/2002US20020132398 Thin film transistors and method of manufacture
09/19/2002US20020132397 Use of atomic oxygen process for improved barrier layer
09/19/2002US20020132396 Semiconductor device and manufacturing method thereof
09/19/2002US20020132395 Body contact in SOI devices by electrically weakening the oxide under the body
09/19/2002US20020132394 Semiconductors
09/19/2002US20020132393 Method for clamping a semiconductor device in a manufacturing process
09/19/2002US20020132392 Semiconductor device and method for manufacturing the same
09/19/2002US20020132385 Method of manufacturing array substrate
09/19/2002US20020132383 Method of manufacturing a semiconductor device
09/19/2002US20020132381 Fabrication method of semiconductor integrated circuit device and testing method
09/19/2002US20020132380 Graphic user interface, which is based on the html/xml page format, is implemented in the at least one display/operator control unit and/or the computing unit
09/19/2002US20020132377 Effective channel length control using ion implant feed forward
09/19/2002US20020132375 Self-aligned, trenchless mangetoresitive random-access memory (MRAM) structure with sidewall containment of MRAM structure
09/19/2002US20020132374 Method for controlling deposition of dielectric films
09/19/2002US20020132194 Ashing a photo-sensitive material over the ruthenium or the ruthenium oxide using a gas mixture containing oxygen gas or ozone gas and nitrogen gas
09/19/2002US20020132193 Developing solution for a photoresist and a method for developing the photoresist
09/19/2002US20020132192 Forming resist pattern layer having a predetermined pattern from resist film of organic material formed on substrate; rinsing by exposing to rinse solution; supplying supercritical carbon dioxide to dry pattern layer; vaporization
09/19/2002US20020132191 Forming silicon layer and mask on semiconductor wafer; spacers are formed around mask; silicon layer not covered by mask or second spacers are removed; mask and the second spacers are removed; silicide layer is fored to form share contact
09/19/2002US20020132186 May be exposed to light using ArF lasers, may have strong resistances to dry etching processes, may possess excellent adhesion to film materials, and may be developed using conventional developers
09/19/2002US20020132185 Copolymer photoresist with improved etch resistance
09/19/2002US20020132184 System and method for developing a photoresist layer with reduced pattern collapse
09/19/2002US20020132183 Organic anti-reflective coating material and its preparation
09/19/2002US20020132180 Photoresist composition
09/19/2002US20020132073 Precision product container
09/19/2002US20020132061 Preparing organic polymer constituent and an inorganic-organic constituent and/or inorganic constituent and applying layer on substrate; removal of inorganic-organic constituent and/or inorganic constituent from layer to form a porous layer
09/19/2002US20020132060 Laser marking techniques
09/19/2002US20020132052 Thermal processing system and methods for forming low-k dielectric films suitable for incorporation into microelectronic devices
09/19/2002US20020132042 Plating catalysts
09/19/2002US20020131913 Decomposing perfluorcompounds contained in a gas and sucking a discharged gas containing acid gases resulting from the decomposition of the perfluorocompounds by a jet stream of an injected gas, thereby ejecting the sucked gas
09/19/2002US20020131912 Method and apparatus for treating perfluorocompounds
09/19/2002US20020131875 Filter unit, chemical liquid supply system, and chemical liquid supply method
09/19/2002US20020131850 Reticle transfer system
09/19/2002US20020131848 Alignment apparatus
09/19/2002US20020131550 Evaluation method and evaluation apparatus for semiconductor device
09/19/2002US20020131304 Twin monos memory cell usage for wide program
09/19/2002US20020131296 Magnetic material memory and information reproducing method of the same
09/19/2002US20020131295 MRAM architecture and system
09/19/2002US20020131291 Interleaved wordline architecture
09/19/2002US20020131289 Metal during pattern for memory devices
09/19/2002US20020131253 Circuit board and method of manufacturing the same, and display device
09/19/2002US20020131246 Defect-free dielectric coatings and preparation thereof using polymeric nitrogenous porogens
09/19/2002US20020131181 Illumination system with raster elements of different sizes
09/19/2002US20020131166 Microscope for inspecting semiconductor wafer
09/19/2002US20020131055 Method and apparatus for the determination of mask rules using scatterometry
09/19/2002US20020131040 System and method for characterizing macro-grating test patterns in advanced lithography and etch processes
09/19/2002US20020131032 Scanning exposure apparatus and device manufacturing method using the same
09/19/2002US20020131030 Projection exposure apparatus and device manufacturing method using the same
09/19/2002US20020131010 Liquid crystal display device and defect repairing method for the same
09/19/2002US20020131003 Active matrix type liquid crystal display device and method of manufacturing the same
09/19/2002US20020131002 Electrode substrate for liquid crystal display panel, method of fabricating the electrode substrate, and liquid crystal display panel
09/19/2002US20020130983 Liquid crystal display
09/19/2002US20020130789 Apparatus and method for non-contact temperature measurement
09/19/2002US20020130785 Semiconductor wafer imaging system
09/19/2002US20020130714 Semiconductor integrated circuit device having an optimal circuit layout to ensure stabilization of internal source voltages without lowering circuit functions and/or operating performance
09/19/2002US20020130712 System and method utilizing on-chip voltage monitoring to manage power consumption
09/19/2002US20020130687 Antifuse reroute of dies
09/19/2002US20020130679 Characteristic evaluation apparatus for insulated gate type transistors
09/19/2002US20020130677 Semiconductor die test carrier having conductive elastomeric interposer
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