| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
|---|
| 09/17/2002 | US6452227 Semiconductor memory device and manufacturing method thereof |
| 09/17/2002 | US6452226 Non-volatile semiconductor memory device and manufacturing method thereof |
| 09/17/2002 | US6452225 Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride |
| 09/17/2002 | US6452224 Method for manufacture of improved deep trench eDRAM capacitor and structure produced thereby |
| 09/17/2002 | US6452223 Methods of fabricating buried digit lines and semiconductor devices including same |
| 09/17/2002 | US6452222 MIS type semiconductor device and method for manufacturing the same |
| 09/17/2002 | US6452221 Enhancement mode device |
| 09/17/2002 | US6452219 Insulated gate bipolar transistor and method of fabricating the same |
| 09/17/2002 | US6452216 Nitride semiconductor light emitting device and apparatus including the same |
| 09/17/2002 | US6452213 Semiconductor device having first, second and third non-crystalline films sequentially formed on insulating base with second film having thermal conductivity not lower than that of first film and not higher than that of third film, and method of manufacturing the same |
| 09/17/2002 | US6452212 Semiconductor device and method for operating the same |
| 09/17/2002 | US6452211 Semiconductor thin film and semiconductor device |
| 09/17/2002 | US6452204 Tunneling magnetoresistance transducer and method for manufacturing the same |
| 09/17/2002 | US6452201 Wafer-mapping method of wafer load port equipment |
| 09/17/2002 | US6452196 Power supply hardening for ion beam systems |
| 09/17/2002 | US6452195 Wafer holding pin |
| 09/17/2002 | US6452194 Radiation source for use in lithographic projection apparatus |
| 09/17/2002 | US6452193 Electron beam exposure apparatus, electron lens, and device manufacturing method |
| 09/17/2002 | US6452178 Method and an apparatus of an inspection system using an electron beam |
| 09/17/2002 | US6452173 Charged particle apparatus |
| 09/17/2002 | US6452117 Method for filling high aspect ratio via holes in electronic substrates and the resulting holes |
| 09/17/2002 | US6452115 Circuit pattern for multi-layer circuit board for mounting electronic parts |
| 09/17/2002 | US6452111 Adhesives and adhesive films |
| 09/17/2002 | US6452110 Patterning microelectronic features without using photoresists |
| 09/17/2002 | US6452091 Method of producing thin-film single-crystal device, solar cell module and method of producing the same |
| 09/17/2002 | US6452087 Photovoltaic device and method of fabricating the same |
| 09/17/2002 | US6452017 Thermally stable trispyrazolylmethanate metal complexes; chemical vapor deposition of such as barium strontium titanate thin films on random access memory devices |
| 09/17/2002 | US6451875 Connecting material for anisotropically electroconductive connection |
| 09/17/2002 | US6451714 Radiant power source |
| 09/17/2002 | US6451713 Semiconductors |
| 09/17/2002 | US6451712 Method for forming a porous dielectric material layer in a semiconductor device and device formed |
| 09/17/2002 | US6451711 Semiconductors, gadolinium oxide |
| 09/17/2002 | US6451710 Method of manufacturing multi-layer printed wiring board |
| 09/17/2002 | US6451709 Methodology of removing misplaced encapsulant for attachment of heat sinks in a chip on board package |
| 09/17/2002 | US6451708 Method of forming contact holes in a semiconductor device |
| 09/17/2002 | US6451707 Method of removing reaction product due to plasma ashing of a resist pattern |
| 09/17/2002 | US6451706 Attenuation of reflecting lights by surface treatment |
| 09/17/2002 | US6451705 Self-aligned PECVD etch mask |
| 09/17/2002 | US6451704 Method for forming PLDD structure with minimized lateral dopant diffusion |
| 09/17/2002 | US6451703 Magnetically enhanced plasma etch process using a heavy fluorocarbon etching gas |
| 09/17/2002 | US6451701 Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors |
| 09/17/2002 | US6451700 Method and apparatus for measuring planarity of a polished layer |
| 09/17/2002 | US6451699 Method and apparatus for planarizing a wafer surface of a semiconductor wafer having an elevated portion extending therefrom |
| 09/17/2002 | US6451698 System and method for preventing electrochemical erosion by depositing a protective film |
| 09/17/2002 | US6451697 Method for abrasive-free metal CMP in passivation domain |
| 09/17/2002 | US6451696 Method for reclaiming wafer substrate and polishing solution compositions therefor |
| 09/17/2002 | US6451695 Depositing a monolayer of metal on the substrate surface by flowing a molecular precursor gas or vapor bearing the metal over a surface, flowing at least one radical species into the chamber and over the surface |
| 09/17/2002 | US6451694 Control of abnormal growth in dichloro silane (DCS) based CVD polycide WSix films |
| 09/17/2002 | US6451693 Double silicide formation in polysicon gate without silicide in source/drain extensions |
| 09/17/2002 | US6451691 Methods of manufacturing a metal pattern of a semiconductor device which include forming nitride layer at exposed sidewalls of Ti layer of the pattern |
| 09/17/2002 | US6451690 Method of forming electrode structure and method of fabricating semiconductor device |
| 09/17/2002 | US6451689 Electroless plating of copper |
| 09/17/2002 | US6451688 Opening of a downwardly protruding window for a dual damascene structure |
| 09/17/2002 | US6451687 Intermetal dielectric layer for integrated circuits |
| 09/17/2002 | US6451686 Control of semiconductor device isolation properties through incorporation of fluorine in peteos films |
| 09/17/2002 | US6451685 Method for multilevel copper interconnects for ultra large scale integration |
| 09/17/2002 | US6451684 Semiconductor device having a conductive layer side surface slope which is at least 90° and method for manufacturing the same |
| 09/17/2002 | US6451683 Damascene structure and method of making |
| 09/17/2002 | US6451682 Method of forming interconnect film |
| 09/17/2002 | US6451681 Method of forming copper interconnection utilizing aluminum capping film |
| 09/17/2002 | US6451679 Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology |
| 09/17/2002 | US6451678 Method of reducing overetch during the formation of a semiconductor device |
| 09/17/2002 | US6451677 Plasma-enhanced chemical vapor deposition of a nucleation layer in a tungsten metallization process |
| 09/17/2002 | US6451676 Method for setting the threshold voltage of a MOS transistor |
| 09/17/2002 | US6451675 Semiconductor device having varied dopant density regions |
| 09/17/2002 | US6451674 Method for introducing impurity into a semiconductor substrate without negative charge buildup phenomenon |
| 09/17/2002 | US6451673 Carrier gas modification for preservation of mask layer during plasma etching |
| 09/17/2002 | US6451672 Method for manufacturing electronic devices in semiconductor substrates provided with gettering sites |
| 09/17/2002 | US6451671 Semiconductor device production method and apparatus |
| 09/17/2002 | US6451670 Substrate processing apparatus, substrate support apparatus, substrate processing method, and substrate fabrication method |
| 09/17/2002 | US6451669 Method of forming insulated metal interconnections in integrated circuits |
| 09/17/2002 | US6451667 Self-aligned double-sided vertical MIMcap |
| 09/17/2002 | US6451666 Method for forming a lower electrode by using an electroplating method |
| 09/17/2002 | US6451665 Method of manufacturing a semiconductor integrated circuit |
| 09/17/2002 | US6451664 Method of making a MIM capacitor with self-passivating plates |
| 09/17/2002 | US6451663 Method of manufacturing a cylindrical storage node in a semiconductor device |
| 09/17/2002 | US6451662 Method of forming low-leakage on-chip capacitor |
| 09/17/2002 | US6451661 DRAM capacitor formulation using a double-sided electrode |
| 09/17/2002 | US6451660 Method of forming bipolar transistors comprising a native oxide layer formed on a substrate by rinsing the substrate in ozonated water |
| 09/17/2002 | US6451659 In semiconductors |
| 09/17/2002 | US6451658 Graded layer for use in semiconductor circuits and method for making same |
| 09/17/2002 | US6451657 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant |
| 09/17/2002 | US6451656 CMOS inverter configured from double gate MOSFET and method of fabricating same |
| 09/17/2002 | US6451655 Electronic power device monolithically integrated on a semiconductor and comprising a first power region and at least a second region as well as an isolation structure of limited planar dimension |
| 09/17/2002 | US6451654 Process for fabricating self-aligned split gate flash memory |
| 09/17/2002 | US6451653 Manufacturing process for the integration in a semiconductor chip of an integrated circuit including a high-density integrated circuit components portion and a high-performance logic integrated circuit components portion |
| 09/17/2002 | US6451652 Method for forming an EEPROM cell together with transistor for peripheral circuits |
| 09/17/2002 | US6451651 Method of manufacturing DRAM device invention |
| 09/17/2002 | US6451650 Low thermal budget method for forming MIM capacitor |
| 09/17/2002 | US6451649 Method for fabricating semiconductor device having a capacitor |
| 09/17/2002 | US6451648 Process for buried-strap self-aligned to deep storage trench |
| 09/17/2002 | US6451647 Semiconductors |
| 09/17/2002 | US6451646 High-k dielectric materials and processes for manufacturing them |
| 09/17/2002 | US6451645 Method for manufacturing semiconductor device with power semiconductor element and diode |
| 09/17/2002 | US6451644 Method of providing a gate conductor with high dopant activation |
| 09/17/2002 | US6451643 Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs |
| 09/17/2002 | US6451642 Method to implant NMOS polycrystalline silicon in embedded FLASH memory applications |
| 09/17/2002 | US6451641 Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material |
| 09/17/2002 | US6451640 Semiconductor device having NMOS and PMOS transistors on common substrate and method of fabricating the same |
| 09/17/2002 | US6451639 Method for forming a gate in a semiconductor device |