| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 02/04/2003 | US6515351 Integrated circuit with borderless contacts |
| 02/04/2003 | US6515350 Protective conformal silicon nitride films and spacers |
| 02/04/2003 | US6515349 Semiconductor device and process for the same |
| 02/04/2003 | US6515348 Semiconductor device with FET MESA structure and vertical contact electrodes |
| 02/04/2003 | US6515347 Wafer level semiconductor device and method of manufacturing the same |
| 02/04/2003 | US6515345 Transient voltage suppressor with diode overlaying another diode for conserving space |
| 02/04/2003 | US6515342 Method and system for providing inorganic vapor surface treatment for photoresist adhesion promotion |
| 02/04/2003 | US6515340 Separation and active region, gate oxide film; electrode coupled to source and drain region |
| 02/04/2003 | US6515339 Method of horizontally growing carbon nanotubes and field effect transistor using the carbon nanotubes grown by the method |
| 02/04/2003 | US6515338 Semiconductor device and manufacturing method therefor |
| 02/04/2003 | US6515337 Input protection circuit connected to projection circuit power source potential line |
| 02/04/2003 | US6515336 Thin film transistors having tapered gate electrode and taped insulating film |
| 02/04/2003 | US6515335 Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
| 02/04/2003 | US6515334 Hybrid circuit and electronic device using same |
| 02/04/2003 | US6515333 Removal of heat from SOI device |
| 02/04/2003 | US6515331 MOSFET structure for use in ESD protection devices |
| 02/04/2003 | US6515330 Power device having vertical current path with enhanced pinch-off for current limiting |
| 02/04/2003 | US6515329 Flash memory device and method of making same |
| 02/04/2003 | US6515328 Semiconductor substrate; an insulating layer over the semiconductor substrate; a floating gate electrode overlying the insulating layer; a dielectric layer substantially free of pitting therein overlying the floating gate electrode; and a |
| 02/04/2003 | US6515327 A memory cell and a method for making the same are provided. The trench capacitor includes a vertical trench formed in a semiconductor, a doping region formed around a low portion of the trench, a collar isolation layer formed on an inner |
| 02/04/2003 | US6515326 Semiconductor memory device and method of fabricating the same |
| 02/04/2003 | US6515325 Methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using |
| 02/04/2003 | US6515323 Ferroelectric memory device having improved ferroelectric characteristics |
| 02/04/2003 | US6515322 Silicon substrate, a gate electrode formed through a gate insulator film on a principal surface of the semiconductor substrate, a pair of source/drain regions formed in a principal surface region of the semiconductor substrate to |
| 02/04/2003 | US6515320 Semiconductor device and method of manufacturing the same including thicker insulating layer on lower part of electrode |
| 02/04/2003 | US6515319 Field-effect-controlled transistor and method for fabricating the transistor |
| 02/04/2003 | US6515318 Charge transfer device |
| 02/04/2003 | US6515316 Partially relaxed channel HEMT device |
| 02/04/2003 | US6515309 LED array chip |
| 02/04/2003 | US6515303 Method of forming vias in silicon carbide and resulting devices and circuits |
| 02/04/2003 | US6515302 Power devices in wide bandgap semiconductor |
| 02/04/2003 | US6515300 Method of making a TFT array with photo-imageable insulating layer over address lines |
| 02/04/2003 | US6515299 Semiconductor device with rod like crystals and a recessed insulation layer |
| 02/04/2003 | US6515293 Method and apparatus for detecting thickness of thin layer formed on a wafer |
| 02/04/2003 | US6515291 Electron beam drawing apparatus and method of the same |
| 02/04/2003 | US6515261 Enhanced lift pin |
| 02/04/2003 | US6515073 Anti-reflective coating-forming composition |
| 02/04/2003 | US6515038 Resist compositions containing polymers having dialkyl malonate groups for use in chemically amplified resists |
| 02/04/2003 | US6514921 Cleaning agent |
| 02/04/2003 | US6514886 Method for elimination of contaminants prior to epitaxy |
| 02/04/2003 | US6514885 Semiconductor device manufacturing method to reduce process induced stress and crystalline defects |
| 02/04/2003 | US6514884 Method for reforming base surface, method for manufacturing semiconductor device and equipment for manufacturing the same |
| 02/04/2003 | US6514883 Method of fabricating semiconductor device |
| 02/04/2003 | US6514882 Aggregate dielectric layer to reduce nitride consumption |
| 02/04/2003 | US6514881 Hybrid porous low-K dielectrics for integrated circuits |
| 02/04/2003 | US6514880 Vaporizing a silicon-containing hydrocarbon compound producing gas for polysiloxane, chemical vapor deposition wherein semiconductor is placed, introducing additive gas (inert and oxidizing), forming film via plasma polymerization |
| 02/04/2003 | US6514879 Configuration of various chemical compound generators coupled to a furnace provides the environment for formation of thin oxides of silicon on a wafer; forming steam from dichloroethylene, oxygen and hydrogen |
| 02/04/2003 | US6514878 Method of fabricating a semiconductor device having a multilayered interconnection structure |
| 02/04/2003 | US6514876 Pre-metal dielectric rapid thermal processing for sub-micron technology |
| 02/04/2003 | US6514875 Chemical method for producing smooth surfaces on silicon wafers |
| 02/04/2003 | US6514874 Method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features |
| 02/04/2003 | US6514873 Method for fabricating semiconductor device |
| 02/04/2003 | US6514872 Method of manufacturing a semiconductor device |
| 02/04/2003 | US6514871 Gate etch process with extended CD trim capability |
| 02/04/2003 | US6514870 In situ wafer heat for reduced backside contamination |
| 02/04/2003 | US6514869 Method for use in manufacturing a semiconductor device |
| 02/04/2003 | US6514868 Method of creating a smaller contact using hard mask |
| 02/04/2003 | US6514867 Method of creating narrow trench lines using hard mask |
| 02/04/2003 | US6514866 Chemically enhanced focused ion beam micro-machining of copper |
| 02/04/2003 | US6514865 Method of reducing interlayer dielectric thickness variation feeding into a planarization process |
| 02/04/2003 | US6514864 Fabrication method for semiconductor integrated circuit device |
| 02/04/2003 | US6514863 Method and apparatus for slurry distribution profile control in chemical-mechanical planarization |
| 02/04/2003 | US6514862 Particles, solvent and a quaternary ammonium compound such as (2-hydroxyethyl)trimethylammonium chloride; improved removal selectivity between a layer to be polished and a silicon nitride stop layer |
| 02/04/2003 | US6514861 Manufacturing a semiconductor wafer according to the process time by process tool |
| 02/04/2003 | US6514860 Integration of organic fill for dual damascene process |
| 02/04/2003 | US6514859 Method of salicide formation with a double gate silicide |
| 02/04/2003 | US6514858 Test structure for providing depth of polish feedback |
| 02/04/2003 | US6514857 Damascene structure fabricated using a layer of silicon-based photoresist material |
| 02/04/2003 | US6514856 Method for forming multi-layered interconnect structure |
| 02/04/2003 | US6514855 Semiconductor device manufacturing method having a porous insulating film |
| 02/04/2003 | US6514854 Method of producing semiconductor integrated circuit device having a plug |
| 02/04/2003 | US6514853 Semiconductor device and a manufacturing process therefor |
| 02/04/2003 | US6514852 Semiconductor device and method of manufacturing the same |
| 02/04/2003 | US6514851 Method of fabrication of multilayer semiconductor wiring structure with reduced alignment mark area |
| 02/04/2003 | US6514850 Interface with dielectric layer and method of making |
| 02/04/2003 | US6514849 Method of forming smaller contact size using a spacer hard mask |
| 02/04/2003 | US6514848 Method for forming an interconnection in a semiconductor element |
| 02/04/2003 | US6514847 Method for making a semiconductor device |
| 02/04/2003 | US6514846 Method of fabricating soldering balls for semiconductor encapsulation |
| 02/04/2003 | US6514844 Sidewall treatment for low dielectric constant (low K) materials by ion implantation |
| 02/04/2003 | US6514843 Method of enhanced oxidation of MOS transistor gate corners |
| 02/04/2003 | US6514842 Low resistance gate flash memory |
| 02/04/2003 | US6514841 Forming diffusion barrier |
| 02/04/2003 | US6514840 Micro heating of selective regions |
| 02/04/2003 | US6514839 ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations |
| 02/04/2003 | US6514838 Method for non mass selected ion implant profile control |
| 02/04/2003 | US6514837 High density plasma chemical vapor deposition apparatus and gap filling method using the same |
| 02/04/2003 | US6514836 Methods of producing strained microelectronic and/or optical integrated and discrete devices |
| 02/04/2003 | US6514835 Stress control of thin films by mechanical deformation of wafer substrate |
| 02/04/2003 | US6514834 Method of manufacturing a semiconductor device having a low leakage current |
| 02/04/2003 | US6514833 Method of inhibiting lateral diffusion between adjacent wells by introducing carbon or fluorine ions into bottom of STI groove |
| 02/04/2003 | US6514831 Nitride read only memory cell |
| 02/04/2003 | US6514830 Method of manufacturing high voltage transistor with modified field implant mask |
| 02/04/2003 | US6514829 Method of fabricating abrupt source/drain junctions |
| 02/04/2003 | US6514828 Method of fabricating a highly reliable gate oxide |
| 02/04/2003 | US6514827 Method for fabricating a dual metal gate for a semiconductor device |
| 02/04/2003 | US6514826 Method of forming a gate electrode in a semiconductor device |
| 02/04/2003 | US6514825 Technique for reducing 1/f noise in MOSFETs |
| 02/04/2003 | US6514824 Semiconductor device with a pair of transistors having dual work function gate electrodes |
| 02/04/2003 | US6514823 Method of making loadless four-transistor memory cell with different gate insulation thicknesses for N-channel drive transistors and P-channel access transistors |