Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2003
02/11/2003US6518170 Multilayer dielectric
02/11/2003US6518169 Semiconductor device and method for fabricating the same
02/11/2003US6518168 Self-assembled monolayer directed patterning of surfaces
02/11/2003US6518167 Method of forming a metal or metal nitride interface layer between silicon nitride and copper
02/11/2003US6518166 Liquid phase deposition of a silicon oxide layer for use as a liner on the surface of a dual damascene opening in a low dielectric constant layer
02/11/2003US6518164 Etching process for forming the trench with high aspect ratio
02/11/2003US6518163 Method for forming bumps, semiconductor device, and solder paste
02/11/2003US6518162 Forming an Ni bump by non-electrolytic plating in an opening of an insulating protecting film formed on an electrode pad on a semiconductor substrate, and removing a plating solution residue
02/11/2003US6518161 Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die
02/11/2003US6518160 Method of manufacturing connection components using a plasma patterned mask
02/11/2003US6518158 Method of manufacturing a semiconductor device including a fuse
02/11/2003US6518157 Methods of planarizing insulating layers on regions having different etching rates
02/11/2003US6518155 Device structure and method for reducing silicide encroachment
02/11/2003US6518154 Method of forming semiconductor devices with differently composed metal-based gate electrodes
02/11/2003US6518153 Method for making gate electrodes of low sheet resistance for embedded dynamic random access memory devices
02/11/2003US6518151 Dual layer hard mask for eDRAM gate etch process
02/11/2003US6518150 Method of manufacturing semiconductor device
02/11/2003US6518149 Semiconductor device and method of manufacturing the same
02/11/2003US6518148 Method for protecting STI structures with low etching rate liners
02/11/2003US6518147 Process for manufacturing an SOI wafer by oxidation of buried channels
02/11/2003US6518146 Semiconductor device structure and method for forming
02/11/2003US6518145 Methods to control the threshold voltage of a deep trench corner device
02/11/2003US6518144 Semiconductor device having trenches and process for same
02/11/2003US6518143 Method for fabricating a lower plate for a capacitor of semiconductor device
02/11/2003US6518142 Fabrication method for MIM capacitive circuit having little leakage current
02/11/2003US6518140 Manufacturing methods for defect removable semiconductor devices
02/11/2003US6518139 Power semiconductor device structure with vertical PNP transistor
02/11/2003US6518137 Method for forming steep spacer in a MOS device
02/11/2003US6518136 Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication
02/11/2003US6518135 Method for forming localized halo implant regions
02/11/2003US6518134 Method for fabricating a semiconductor device with an air tunnel formed in the lower part of a transistor channel
02/11/2003US6518133 Method for fabricating a small dimensional gate with elevated source/drain structures
02/11/2003US6518131 Method for fabricating mask ROM
02/11/2003US6518130 Method for forming a semiconductor device having a DRAM region and a logic region on the substrate
02/11/2003US6518129 Manufacture of trench-gate semiconductor devices
02/11/2003US6518128 Trench MOSFET with double-diffused body profile
02/11/2003US6518126 Method of forming and operating trench split gate non-volatile flash memory cell structure
02/11/2003US6518125 Method for forming flash memory with high coupling ratio
02/11/2003US6518124 Method of fabricating semiconductor device
02/11/2003US6518123 Split gate field effect transistor (FET) device with annular floating gate electrode and method for fabrication thereof
02/11/2003US6518122 Low voltage programmable and erasable flash EEPROM
02/11/2003US6518121 Boride electrodes and barriers for cell dielectrics
02/11/2003US6518120 Capacitor and method of manufacturing the same
02/11/2003US6518119 Strap with intrinsically conductive barrier
02/11/2003US6518118 Structure and process for buried bitline and single sided buried conductor formation
02/11/2003US6518117 Methods of forming nitrogen-containing masses, silicon nitride layers, and capacitor constructions
02/11/2003US6518114 Method of forming an insulating zone
02/11/2003US6518113 Doping of thin amorphous silicon work function control layers of MOS gate electrodes
02/11/2003US6518112 High performance, low power vertical integrated CMOS devices
02/11/2003US6518111 Method for manufacturing and structure of semiconductor device with dielectric diffusion source and CMOS integration
02/11/2003US6518110 Capacitance coupling between the source and the floating gate forms a channel in the substrate, which is injected with hot electrons
02/11/2003US6518109 Technique to produce isolated junctions by forming an insulation layer
02/11/2003US6518108 Electronic device and a method for making the same
02/11/2003US6518107 Non-arsenic N-type dopant implantation for improved source/drain interfaces with nickel silicides
02/11/2003US6518106 Semiconductor device and a method therefor
02/11/2003US6518104 Method of manufacturing a semiconductor device by thermal oxidation of an impurity doped amorphous semiconductor film
02/11/2003US6518103 Method for fabricating NROM with ONO structure
02/11/2003US6518102 Method for manufacturing transistor semiconductor devices with step of annealing to getter metal with phosphorous
02/11/2003US6518099 Plated leadframes with cantilevered leads
02/11/2003US6518097 Method for fabricating wafer-level flip chip package using pre-coated anisotropic conductive adhesive
02/11/2003US6518096 Interconnect assembly and Z-connection method for fine pitch substrates
02/11/2003US6518095 Process for producing semiconductor device
02/11/2003US6518094 Center bond flip-chip semiconductor device and method of making it
02/11/2003US6518093 Semiconductor device and method for manufacturing same
02/11/2003US6518092 Semiconductor device and method for manufacturing
02/11/2003US6518091 Method of making anisotropic conductive elements for use in microelectronic packaging
02/11/2003US6518089 Flip chip semiconductor device in a molded chip scale package (CSP) and method of assembly
02/11/2003US6518088 Polymer stud grid array
02/11/2003US6518084 Method of producing a micromechanical structure for a micro-electromechanical element
02/11/2003US6518082 Method for fabricating nitride semiconductor device
02/11/2003US6518081 Method of making TFT-based pixel structure
02/11/2003US6518079 Separation method for gallium nitride devices on lattice-mismatched substrates
02/11/2003US6518075 Method of forming S/D extension regions and pocket regions based on formulated relationship between design and measured values of gate length
02/11/2003US6518074 Backside IC device preparation process
02/11/2003US6518072 Deposited screen oxide for reducing gate edge lifting
02/11/2003US6518070 Process of forming a semiconductor device and a semiconductor device
02/11/2003US6518030 Non-infectious, retrovirus-like particles comprise an assembly of an env gene product, a pol gene product and a gag gene product contain an antigenic marker which is non-retroviral or non-HIV retroviral. In one embodiment, the
02/11/2003US6518022 Method for enhancing the hybridization efficiency of target nucleic acids using a self-addressable, self-assembling microelectronic device
02/11/2003US6517999 Method of removing photoresist film
02/11/2003US6517998 Method for removing photoresist film and apparatus used therefor
02/11/2003US6517995 Fabrication of finely featured devices by liquid embossing
02/11/2003US6517993 Radiation transparent; sensitivity
02/11/2003US6517983 Aberration estimating mask pattern
02/11/2003US6517982 Mask set for use in phase shift photolithography technique which is suitable to form random patterns, and method of exposure process using the same
02/11/2003US6517977 Semiconductors
02/11/2003US6517951 Smokeless
02/11/2003US6517924 Laminated body and method for producing the same
02/11/2003US6517913 Pumping etching exhaust gases from processing chamber to fluid conduit containing oxidizing agent; forming a plasma for conversion to less hazardous gaseous products and byproducts
02/11/2003US6517911 Process for the formation of silicon oxide films
02/11/2003US6517894 Method for plating a first layer on a substrate and a second layer on the first layer
02/11/2003US6517738 Acid blend for removing etch residue
02/11/2003US6517697 Anodizing method
02/11/2003US6517691 Substrate processing system
02/11/2003US6517670 Etching and cleaning apparatus
02/11/2003US6517668 Method and apparatus for endpointing a chemical-mechanical planarization process
02/11/2003US6517667 Apparatus for polishing a semiconductor wafer
02/11/2003US6517666 Automatic decapsulation system utilizing an integrated spacer/protection plate
02/11/2003US6517662 Placing an adhesive comprising a microporous film substrate and a curable adhesive, over flexible substrate, disposing a stiffener over adhesive and placing a compression plate over it, and curing curable adhesive
02/11/2003US6517656 Method of making an integrated circuit package using a batch step for curing a die attachment film and a tool system for performing the method
02/11/2003US6517642 Method and apparatus of producing thin film of metal or metal compound
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