| Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974) |
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| 02/11/2003 | US6518678 Apparatus and method for reducing interposer compression during molding process |
| 02/11/2003 | US6518677 Semiconductor flip-chip package and method for the fabrication thereof |
| 02/11/2003 | US6518676 Metal interconnections and active matrix substrate using the same |
| 02/11/2003 | US6518675 Wafer level package and method for manufacturing the same |
| 02/11/2003 | US6518674 For use in test and burn-in, and subsequent removal without damaging the solder balls, by using first and second volumes of fusible material with melting points such that first volume is not melted when first and second are joined |
| 02/11/2003 | US6518671 An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying |
| 02/11/2003 | US6518670 Electrically porous on-chip decoupling/shielding layer |
| 02/11/2003 | US6518669 Semiconductor device including a pad and a method of manufacturing the same |
| 02/11/2003 | US6518668 Multiple seed layers for metallic interconnects |
| 02/11/2003 | US6518667 Semiconductor package using micro balls and production method thereof |
| 02/11/2003 | US6518666 Circuit board reducing a warp and a method of mounting an integrated circuit chip |
| 02/11/2003 | US6518665 Enhanced underfill adhesion |
| 02/11/2003 | US6518664 Semiconductor integrated circuit device and manufacturing method of that |
| 02/11/2003 | US6518662 Method of assembling a semiconductor chip package |
| 02/11/2003 | US6518654 Packages for semiconductor die |
| 02/11/2003 | US6518653 Lead frame and semiconductor device |
| 02/11/2003 | US6518651 Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| 02/11/2003 | US6518649 Tape carrier type semiconductor device with gold/gold bonding of leads to bumps |
| 02/11/2003 | US6518648 Superconductor barrier layer for integrated circuit interconnects |
| 02/11/2003 | US6518646 Semiconductor device with variable composition low-k inter-layer dielectric and method of making |
| 02/11/2003 | US6518645 SOI-type semiconductor device and method of forming the same |
| 02/11/2003 | US6518644 A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100 degrees C. above the deposition temperature, |
| 02/11/2003 | US6518642 Contact to passive device of a semiconductor circuit device, the passive device being, for example, a resistor, an inductor, a fuse or the like. Adjacent, spaced, elevated, so-called dummy pattern (shoulder) regions are formed under |
| 02/11/2003 | US6518641 Deep slit isolation with controlled void |
| 02/11/2003 | US6518636 Semiconductor MISFET |
| 02/11/2003 | US6518635 Semiconductor device and manufacturing method thereof |
| 02/11/2003 | US6518634 A method of forming a capacitor and transistor are disclosed. a substrate having a semiconductor material on a firstsurface is provided. A layer of strontium nitride is then deposited over the first surface and a gate electrode formed over the |
| 02/11/2003 | US6518633 Semiconductor device and method for manufacturing the same |
| 02/11/2003 | US6518631 Multi-Thickness silicide device formed by succesive spacers |
| 02/11/2003 | US6518630 Thin film transistor array substrate for liquid crystal display and method for fabricating same |
| 02/11/2003 | US6518629 Semiconductor device and process for producing the device |
| 02/11/2003 | US6518628 Integrated CMOS circuit configuration, and production of same |
| 02/11/2003 | US6518627 Semiconductor device and method of manufacturing the same |
| 02/11/2003 | US6518626 Method of forming low dielectric silicon oxynitride spacer films highly selective of etchants |
| 02/11/2003 | US6518625 Semiconductor device |
| 02/11/2003 | US6518624 Trench-gate power semiconductor device preventing latch-up and method for fabricating the same |
| 02/11/2003 | US6518623 Semiconductor device having a buried-channel MOS structure |
| 02/11/2003 | US6518622 Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor |
| 02/11/2003 | US6518621 Trench DMOS transistor having reduced punch-through |
| 02/11/2003 | US6518620 EEPROM memory cell with increased dielectric integrity |
| 02/11/2003 | US6518619 Virtual-ground, split-gate flash memory cell arrangements and method for producing same |
| 02/11/2003 | US6518618 Integrated memory cell and method of fabrication |
| 02/11/2003 | US6518616 Vertical gate top engineering for improved GC and CB process windows |
| 02/11/2003 | US6518615 Method and structure for high capacitance memory cells |
| 02/11/2003 | US6518614 Embedded one-time programmable non-volatile memory using prompt shift device |
| 02/11/2003 | US6518613 A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the |
| 02/11/2003 | US6518612 Semiconductor memory device using hemispherical grain silicon for bottom electrodes |
| 02/11/2003 | US6518611 Capacitor array structure for semiconductor devices |
| 02/11/2003 | US6518610 Rhodium-rich oxygen barriers |
| 02/11/2003 | US6518609 Niobium or vanadium substituted strontium titanate barrier intermediate a silicon underlayer and a functional metal oxide film |
| 02/11/2003 | US6518608 Semiconductor integrated circuit device with enhanced protection from electrostatic breakdown |
| 02/11/2003 | US6518606 Semiconductor device permitting electrical measurement of contact alignment error |
| 02/11/2003 | US6518605 Solid state imaging pickup device and method for manufacturing the same |
| 02/11/2003 | US6518603 Selective electrochemical process for creating semiconductor nano- and micro-patterns |
| 02/11/2003 | US6518602 Nitride compound semiconductor light emitting device and method for producing the same |
| 02/11/2003 | US6518596 Formation of contacts on thin films |
| 02/11/2003 | US6518594 Semiconductor devices |
| 02/11/2003 | US6518593 Integrated circuit and method of designing integrated circuit |
| 02/11/2003 | US6518592 Apparatus, method and pattern for evaluating semiconductor device characteristics |
| 02/11/2003 | US6518591 Contact monitor, method of forming same and method of analizing contact-, via- and/or trench-forming processes in an integrated circuit |
| 02/11/2003 | US6518589 Dual mode FET & logic circuit having negative differential resistance mode |
| 02/11/2003 | US6518588 Magnetic random access memory with thermally stable magnetic tunnel junction cells |
| 02/11/2003 | US6518571 Through-the-substrate investigation of flip-chip IC's |
| 02/11/2003 | US6518548 Unifying the temperature of the substrate and capable of shortening the temperature elevation time (temperature lowering time), the substrate temperature control system is equipped with a temperature control plate (heating or cooling |
| 02/11/2003 | US6518547 A heat treatment apparatus rotating a substrate and irradiating said substrate with light for performing heat treatment, comprising: a lamp group having a plurality of lamps, each irradiating said substrate with light, arranged to |
| 02/11/2003 | US6518502 Ceramic multilayer circuit boards mounted on a patterned metal support substrate |
| 02/11/2003 | US6518392 Encapped oligomeric polybenzoxazole, polybenzothiazole, polyamic acid or polyamic acid esters as precursors for dielectric compounds |
| 02/11/2003 | US6518390 Precursor of a heat resistant resin, heat resistant resin, insulating film and semiconductor device |
| 02/11/2003 | US6518206 Method for etching an anti-reflective coating |
| 02/11/2003 | US6518205 Multifunctional reagents for the surface modification of nanoporous silica films |
| 02/11/2003 | US6518204 Curable organopolysiloxane composition and method of manufacturing semiconductor devices with the use of the aforementioned composition |
| 02/11/2003 | US6518203 Passivating dielectric layer with activated nitrogen atoms, then forming metal nitride film on the nitrogen passivated dielectric layer |
| 02/11/2003 | US6518202 Feeding water to the surface of a semiconductor wafer and forming a thin oxide film as a gate insulating film of an transistor |
| 02/11/2003 | US6518201 Method for fabricating semiconductor integrated circuit device |
| 02/11/2003 | US6518200 Graded composite layer and method for fabrication thereof |
| 02/11/2003 | US6518199 Method and system for coating and developing |
| 02/11/2003 | US6518198 Electroless deposition of doped noble metals and noble metal alloys |
| 02/11/2003 | US6518197 Method for manufacturing semiconductor device |
| 02/11/2003 | US6518196 Method of manufacturing semiconductor device |
| 02/11/2003 | US6518195 Plasma reactor using inductive RF coupling, and processes |
| 02/11/2003 | US6518194 Intermediate transfer layers for nanoscale pattern transfer and nanostructure formation |
| 02/11/2003 | US6518193 Substrate processing system |
| 02/11/2003 | US6518192 Two etchant etch method |
| 02/11/2003 | US6518191 Method for etching organic film, method for fabricating semiconductor device and pattern formation method |
| 02/11/2003 | US6518188 Apparatus and methods for chemical-mechanical polishing of semiconductor wafers |
| 02/11/2003 | US6518186 Use of residual organic compounds to facilitate gate break on a carrier substrate for a semiconductor device |
| 02/11/2003 | US6518185 Integration scheme for non-feature-size dependent cu-alloy introduction |
| 02/11/2003 | US6518184 Enhancement of an interconnect |
| 02/11/2003 | US6518183 Hillock inhibiting method for forming a passivated copper containing conductor layer |
| 02/11/2003 | US6518181 Conductive material for integrated circuit fabrication |
| 02/11/2003 | US6518180 Method for fabricating semiconductor device and method for forming mask suitable therefor |
| 02/11/2003 | US6518179 Method of controlling hillock formation of platinum thin film of semiconductor memory device by ion bombardment |
| 02/11/2003 | US6518178 Method for forming a field effect transistor having increased breakdown voltage |
| 02/11/2003 | US6518177 Method of manufacturing a semiconductor device |
| 02/11/2003 | US6518176 Method of selective formation of a barrier layer for a contact level via |
| 02/11/2003 | US6518175 Process for reducing critical dimensions of contact holes, vias, and trench structures in integrated circuits |
| 02/11/2003 | US6518174 Combined resist strip and barrier etch process for dual damascene structures |
| 02/11/2003 | US6518173 Method for avoiding fluorine contamination of copper interconnects |
| 02/11/2003 | US6518172 Method for applying uniform pressurized film across wafer |
| 02/11/2003 | US6518171 Dual damascene process using a low k interlayer for forming vias and trenches |