Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2003
02/18/2003US6522005 Integrated circuit device comprising low dielectric constant material for reduced cross talk
02/18/2003US6522004 Semiconductor integrated circuit device
02/18/2003US6522003 Semiconductor device and method of manufacturing the same
02/18/2003US6522002 Semiconductor device and method of manufacturing the same
02/18/2003US6522001 Local interconnect structures and methods for making the same
02/18/2003US6522000 Method for making a semiconductor device having copper conductive layers
02/18/2003US6521999 Transparent electrode film and group III nitride semiconductor device
02/18/2003US6521998 Electrode structure for nitride III-V compound semiconductor devices
02/18/2003US6521996 Ball limiting metallurgy for input/outputs and methods of fabrication
02/18/2003US6521995 Wafer-level package
02/18/2003US6521988 Device for packaging electronic components
02/18/2003US6521981 Semiconductor device and manufacturing method thereof
02/18/2003US6521980 Controlling packaging encapsulant leakage
02/18/2003US6521979 Member for semiconductor package and semiconductor package using the same, and fabrication method thereof
02/18/2003US6521977 Deuterium reservoirs and ingress paths
02/18/2003US6521975 Scribe street seals in semiconductor devices and method of fabrication
02/18/2003US6521974 Bipolar transistor and manufacturing method thereof
02/18/2003US6521973 Semiconductor device with integrated power transistor and suppression diode
02/18/2003US6521970 Chip scale package with compliant leads
02/18/2003US6521969 Semiconductor device and method of producing the same
02/18/2003US6521964 Device having spacers for improved salicide resistance on polysilicon gates
02/18/2003US6521963 Semiconductor device and method of manufacturing semiconductor device
02/18/2003US6521962 High voltage MOS devices
02/18/2003US6521961 Semiconductor device using a barrier layer between the gate electrode and substrate and method therefor
02/18/2003US6521960 Column transistor for semiconductor devices
02/18/2003US6521957 Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell
02/18/2003US6521956 Semiconductor device having contact of Si-Ge combined with cobalt silicide
02/18/2003US6521955 Semiconductor device including memory cells and manufacturing method thereof
02/18/2003US6521954 Semiconductor device and manufacturing method thereof
02/18/2003US6521953 Lateral edge of photoresist mask is shifted after doping
02/18/2003US6521950 Ultra-high resolution liquid crystal display on silicon-on-sapphire
02/18/2003US6521949 SOI transistor with polysilicon seed
02/18/2003US6521947 Method of integrating substrate contact on SOI wafers with STI process
02/18/2003US6521945 Method and composite for decreasing charge leakage
02/18/2003US6521944 Capacitive coupling oriented along sidewall of trench; semiconductors
02/18/2003US6521943 Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture
02/18/2003US6521942 Electrically programmable memory cell
02/18/2003US6521941 Non-volatile memory device and fabrication method thereof
02/18/2003US6521940 High density electronic circuit modules
02/18/2003US6521939 Interlevel dielectric overlaying electrode and diffusion junctions; two-dimensional array of contact openings; semiconductors
02/18/2003US6521938 Dynamic-type semiconductor memory device
02/18/2003US6521937 Memory cell device including overlapping capacitors
02/18/2003US6521935 Mos transistor and dram cell configuration
02/18/2003US6521934 Semiconductor device with a plurality of elements having different heights
02/18/2003US6521933 Semiconductor device and method of manufacturing the same
02/18/2003US6521932 Semiconductor device with copper wiring connected to storage capacitor
02/18/2003US6521931 Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme
02/18/2003US6521930 Semiconductor device having Ta2O5 thin film
02/18/2003US6521929 Semiconductor device having ferroelectric memory cells and method of manufacturing the same
02/18/2003US6521928 Ferroelectric capacitor array and method for manufacturing ferroelectric memory
02/18/2003US6521927 Semiconductor device and method for the manufacture thereof
02/18/2003US6521924 Image sensor incorporating therein a capacitor structure and method for the manufacture thereof
02/18/2003US6521923 Microwave field effect transistor structure on silicon carbide substrate
02/18/2003US6521922 Passivation film on a semiconductor wafer
02/18/2003US6521919 Semiconductor device of reduced thermal resistance and increased operating area
02/18/2003US6521912 Semiconductor device
02/18/2003US6521911 High dielectric constant metal silicates formed by controlled metal-surface reactions
02/18/2003US6521909 Thin film semiconductor device containing polycrystalline Si-Ge alloy and method for producing thereof
02/18/2003US6521903 Deflection noise reduction in charged particle beam lithography
02/18/2003US6521901 System to reduce heat-induced distortion of photomasks during lithography
02/18/2003US6521900 Alignment marks for charged-particle-beam microlithography, and alignment methods using same
02/18/2003US6521895 Wide dynamic range ion beam scanners
02/18/2003US6521890 Focused ion beam machining method and focused ion beam machining apparatus
02/18/2003US6521889 Dust particle inspection apparatus, and device manufacturing method using the same
02/18/2003US6521877 Optical arrangement having improved temperature distribution within an optical element
02/18/2003US6521853 Method and apparatus for sorting semiconductor devices
02/18/2003US6521827 Sheet manufacturing method, sheet, sheet manufacturing apparatus, and solar cell
02/18/2003US6521574 Copper-based metal polishing solution and method for manufacturing a semiconductor device
02/18/2003US6521550 Process for manufacturing semiconductor integrated circuit device including treatment of gas used in the process
02/18/2003US6521549 Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuit
02/18/2003US6521548 Method of forming a spin-on-passivation layer
02/18/2003US6521547 Coating photoresist, forming an opening, dry etching oxygen plasma ashing
02/18/2003US6521546 Forming hardmask by applying electric field to fluoro-organosilane and oxidizing gas
02/18/2003US6521545 Method of a surface treatment on a fluorinated silicate glass film
02/18/2003US6521544 Method of forming an ultra thin dielectric film
02/18/2003US6521542 Method for forming dual damascene structure
02/18/2003US6521541 Surface preparation of substances for continuous convective assembly of fine particles
02/18/2003US6521540 Method for making self-aligned contacts to source/drain without a hard mask layer
02/18/2003US6521539 Selective etch method for selectively etching a multi-layer stack layer
02/18/2003US6521538 Method of forming a trench with a rounded bottom in a semiconductor device
02/18/2003US6521537 Modification to fill layers for inlaying semiconductor patterns
02/18/2003US6521536 Planarization process
02/18/2003US6521534 Treatment of exposed silicon and silicon dioxide surfaces
02/18/2003US6521533 Method for producing a copper connection
02/18/2003US6521532 Method for making integrated circuit including interconnects with enhanced electromigration resistance
02/18/2003US6521531 Method for selectively growing a conductive film to fill a contact hole
02/18/2003US6521529 HDP treatment for reduced nickel silicide bridging
02/18/2003US6521527 Semiconductor device and method of fabricating the same
02/18/2003US6521526 Protection layer on a semiconductor substrate in which a control gate is formed in a stack structure of doped poly Si and etches only a given portion of the protection layer in a subsequent process to form a contact hole.
02/18/2003US6521525 Electro-optic device, drive substrate for electro-optic device and method of manufacturing the same
02/18/2003US6521524 Via filled dual damascene structure with middle stop layer and method for making the same
02/18/2003US6521523 Method for forming selective protection layers on copper interconnects
02/18/2003US6521522 Method for forming contact holes for metal interconnection in semiconductor devices
02/18/2003US6521521 Bonding pad structure and method for fabricating the same
02/18/2003US6521520 Semiconductor wafer arrangement and method of processing a semiconductor wafer
02/18/2003US6521519 MIS transistor and manufacturing method thereof
02/18/2003US6521518 Method of eliminating weakness caused by high density plasma dielectric layer
02/18/2003US6521517 Method of fabricating a gate electrode using a second conductive layer as a mask in the formation of an insulating layer by oxidation of a first conductive layer
02/18/2003US6521515 Deeply doped source/drains for reduction of silicide/silicon interface roughness
02/18/2003US6521514 Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates
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