Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2003
06/03/2003US6573739 IC testing apparatus
06/03/2003US6573738 Multi-layered probe for a probecard
06/03/2003US6573735 Reliability of vias and diagnosis by e-beam probing
06/03/2003US6573713 Transpinnor-based switch and applications
06/03/2003US6573613 Semiconductor memory device having cell plate electrodes allowing independent power supply for each redundant replacement unit
06/03/2003US6573612 Resin-encapsulated semiconductor device including resin extending beyond edge of substrate
06/03/2003US6573610 Substrate of semiconductor package for flip chip package
06/03/2003US6573607 Semiconductor device and manufacturing method thereof
06/03/2003US6573605 Semiconductor integrated circuit device, design method for semiconductor integrated circuit device, design aiding device for semiconductor integrated circuit device, program, and program recording medium
06/03/2003US6573604 Semiconductor device carrying memory and logic circuit on a chip and method of manufacturing the same
06/03/2003US6573603 Semiconductor device, and method of manufacturing the same
06/03/2003US6573602 Semiconductor device with a self-aligned contact and a method of manufacturing the same
06/03/2003US6573601 Integrated circuit contact
06/03/2003US6573599 Electrical contact for compound semiconductor device and method for forming same
06/03/2003US6573598 Semiconductor device and method of fabricating the same
06/03/2003US6573596 Non-rectangular thermo module wafer cooling device using the same
06/03/2003US6573594 BGA semiconductor device using insulating film
06/03/2003US6573592 Semiconductor die packages with standard ball grid array footprint and method for assembling the same
06/03/2003US6573591 Spherical semiconductor device and method of mounting the same on a substrate
06/03/2003US6573589 Semiconductor device and process for fabricating the same
06/03/2003US6573588 Capacitance element
06/03/2003US6573587 Metal oxide capacitor with hydrogen diffusion blocking covering
06/03/2003US6573586 Semiconductor device
06/03/2003US6573583 Gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating
06/03/2003US6573582 Semiconductor device
06/03/2003US6573577 Semiconductor device and method for fabricating the same
06/03/2003US6573576 Semiconductor device and method for fabricating the same
06/03/2003US6573575 DRAM MOS field effect transistors with thresholds determined by differential gate doping
06/03/2003US6573574 Cell array region of a NOR-type mask ROM device and fabricating method therefor
06/03/2003US6573573 Mask ROM and method for fabricating the same
06/03/2003US6573572 Damascene structure and method of making
06/03/2003US6573571 Semiconductor structure including metal nitride and metal silicide layers over active area and gate stack
06/03/2003US6573570 Semiconductor device having contact electrode to semiconductor substrate
06/03/2003US6573565 Method and structure for providing improved thermal conduction for silicon semiconductor devices
06/03/2003US6573564 Device having high mass production performance and high reliability and reproducibility by simple fabrication steps, in a constitution of a semiconductor device of a bottom gate type formed by a semiconductor layer having a crystal
06/03/2003US6573563 SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs
06/03/2003US6573562 First conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the
06/03/2003US6573561 Vertical MOSFET with asymmetrically graded channel doping
06/03/2003US6573559 Transistor and method of manufacturing the same
06/03/2003US6573558 High-voltage vertical transistor with a multi-layered extended drain structure
06/03/2003US6573557 EEPROM cell having reduced cell area
06/03/2003US6573556 Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash memory
06/03/2003US6573555 Source side injection programming and tip erasing P-channel split gate flash memory cell
06/03/2003US6573554 Localized masking for semiconductor structure development
06/03/2003US6573553 Semiconductor device and method for fabricating the same
06/03/2003US6573552 Method to form hemispherical grained polysilicon
06/03/2003US6573551 Self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a
06/03/2003US6573550 Semiconductor with high-voltage components and low-voltage components on a shared die
06/03/2003US6573548 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
06/03/2003US6573547 Method for forming cell capacitor for high-integrated DRAMs
06/03/2003US6573546 Semiconductor integrated circuit device and process for manufacturing the same
06/03/2003US6573545 Semiconductor memory device for eliminating floating body effect and method of fabricating the same
06/03/2003US6573544 Data input/output line structure having reduced resistance
06/03/2003US6573542 Capacitor electrodes arrangement with oxygen iridium between silicon and oxygen barrier layer
06/03/2003US6573540 Semiconductor device and method for fabricating the same
06/03/2003US6573539 Heterojunction bipolar transistor with silicon-germanium base
06/03/2003US6573534 Silicon carbide semiconductor device
06/03/2003US6573533 Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment
06/03/2003US6573532 Thin film transistor array panel for liquid crystal display
06/03/2003US6573531 Systems and methods using sequential lateral solidification for producing single or polycrystalline silicon thin films at low temperatures
06/03/2003US6573529 Two Field Effect Transistors with different device characteristics, a common input terminal, and output terminals A signal transmitting FET has a gate width of 500 mu m and a signal receiving FET has a gate width of 400 mu m. A resistor
06/03/2003US6573522 Locator pin integrated with sensor for detecting semiconductor substrate carrier
06/03/2003US6573520 Electron beam lithography system
06/03/2003US6573519 Electron beam exposure apparatus, adjusting method, and block mask for adjustment
06/03/2003US6573518 Bi mode ion implantation with non-parallel ion beams
06/03/2003US6573517 Ion implantation apparatus
06/03/2003US6573516 Electron-beam lithography method and electron-beam lithography system
06/03/2003US6573515 Charged-particle-beam projection-exposure apparatus and methods exhibiting improved alignment and registration of projected pattern portions
06/03/2003US6573514 Method for aligning electron beam projection lithography tool
06/03/2003US6573508 Electron beam exposing method
06/03/2003US6573504 Infrared sensor and manufacturing method thereof
06/03/2003US6573499 Microstructured pattern inspection method
06/03/2003US6573482 Heating device, liquid processing apparatus using the heating device and method of detecting failure thereof
06/03/2003US6573480 Reducing or eliminating side lobes in patterned resist coatings. The system heats the resist briefly to induce the resist to flow. The system allows the resist to flow long enough for the side lobes to level, but not corrupt the resist
06/03/2003US6573473 Method and system for precisely positioning a waist of a material-processing laser beam to process microstructures within a laser-processing site
06/03/2003US6573471 Welding method for semiconductor materials
06/03/2003US6573458 Printed circuit board
06/03/2003US6573211 Perovskite mixed oxide
06/03/2003US6573202 Four-terminal system for reading the state of a phase qubit
06/03/2003US6573201 Method and apparatus for protection of substrate surface
06/03/2003US6573199 Methods of treating dielectric materials with oxygen, and methods of forming capacitor constructions
06/03/2003US6573198 Earthquake protection for semiconductor processing equipment
06/03/2003US6573197 Thermally stable poly-Si/high dielectric constant material interfaces
06/03/2003US6573196 Method of depositing organosilicate layers
06/03/2003US6573195 Method for manufacturing a semiconductor device by performing a heat-treatment in a hydrogen atmosphere
06/03/2003US6573194 Method of growing surface aluminum nitride on aluminum films with low energy barrier
06/03/2003US6573193 Ozone-enhanced oxidation for high-k dielectric semiconductor devices
06/03/2003US6573192 Dual thickness gate oxide fabrication method using plasma surface treatment
06/03/2003US6573191 Insulating film forming method and insulating film forming apparatus
06/03/2003US6573190 Dry etching device and dry etching method
06/03/2003US6573189 Manufacture method of metal bottom ARC
06/03/2003US6573188 End point detection method for forming a patterned silicon layer
06/03/2003US6573187 Method of forming dual damascene structure
06/03/2003US6573186 Method for forming plug of semiconductor device
06/03/2003US6573185 Manufacture of a semiconductor device
06/03/2003US6573184 Apparatus and method for depositing thin film on wafer using atomic layer deposition
06/03/2003US6573183 Method and apparatus for controlling contamination during the electroplating deposition of metals onto a semiconductor wafer surface
06/03/2003US6573182 Chemical vapor deposition using organometallic precursors
06/03/2003US6573181 Method of forming contact structures using nitrogen trifluoride preclean etch process and a titanium chemical vapor deposition step
06/03/2003US6573180 PECVD method of forming a tungsten silicide layer on a polysilicon layer
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