Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2003
07/29/2003US6600557 Treating with aqueous etch solution of hydrofluoric acid and permanganate oxidizer to increase gloss of unpolished silicon wafer; chemical mechanical polishing
07/29/2003US6600551 Programmable photolithographic mask system and method
07/29/2003US6600541 Liquid crystal display
07/29/2003US6600523 Structure of storage capacitor on common of TFT-LCD panel and fabrication method thereof
07/29/2003US6600428 Radio frequency data communications device
07/29/2003US6600362 Method and circuits for parallel sensing of current in a field effect transistor (FET)
07/29/2003US6600361 Semiconductor device
07/29/2003US6600360 Semiconductor integrated circuit
07/29/2003US6600337 Line segmentation in programmable logic devices having redundancy circuitry
07/29/2003US6600329 Method for inspecting electrical properties of a wafer and apparatus therefor
07/29/2003US6600305 Voltage generating circuit and reference voltage source circuit employing field effect transistors
07/29/2003US6600234 Mounting structure having columnar electrodes and a sealing film
07/29/2003US6600233 Integrated circuit package with surface mounted pins on an organic substrate
07/29/2003US6600232 Flip-chip semiconductor package structure and process for fabricating the same
07/29/2003US6600231 Functional device unit and method of producing the same
07/29/2003US6600230 Depositing seed layer on surface by sputtering, exposing to hydrogen gase during annealing, plating metal; resistivity; semiconductors; dielectrics; wiring structures
07/29/2003US6600229 Planarizers for spin etch planarization of electronic components
07/29/2003US6600228 Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule
07/29/2003US6600227 System and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package
07/29/2003US6600225 Semiconductor device with elongated interconnecting member and fabrication method thereof
07/29/2003US6600224 Thin film attachment to laminate using a dendritic interconnection
07/29/2003US6600221 Semiconductor device with stacked semiconductor chips
07/29/2003US6600218 Semiconductor device
07/29/2003US6600217 Mounting substrate and mounting method for semiconductor device
07/29/2003US6600213 Semiconductor structure and package including a chip having chamfered edges
07/29/2003US6600212 Semiconductor device and method of fabricating the same
07/29/2003US6600211 Bipolar transistor constructions
07/29/2003US6600210 Semiconductor device and method of manufacturing the same
07/29/2003US6600209 Mesh capacitor structure in an integrated circuit
07/29/2003US6600208 Versatile system for integrated circuit containing shielded inductor
07/29/2003US6600207 Structure to reduce line-line capacitance with low K material
07/29/2003US6600205 Method for making low voltage transistors with increased breakdown voltage to substrate having three different MOS transistors
07/29/2003US6600204 Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same
07/29/2003US6600203 Semiconductor device with silicon carbide suppression layer for preventing extension of micropipe
07/29/2003US6600200 MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors
07/29/2003US6600199 Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity
07/29/2003US6600198 Electrostatic discharge protection circuit for a semiconductor device
07/29/2003US6600197 Thin film transistor having a heat sink that exhibits a high degree of heat dissipation effect
07/29/2003US6600196 Thin film transistor, and manufacturing method thereof
07/29/2003US6600195 Semiconductor device
07/29/2003US6600193 Trench MOSFET having implanted drain-drift region
07/29/2003US6600192 High speed switching; silicon carbide substrate; depletion layer expands in channel region; high withstand voltage in off state
07/29/2003US6600191 Method of fabricating conductive straps to interconnect contacts to corresponding digit lines by employing an angled sidewall implant and semiconductor devices fabricated thereby
07/29/2003US6600190 Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions
07/29/2003US6600189 Semiconductor device and semiconductor device manufacturing method
07/29/2003US6600188 EEPROM with a neutralized doping at tunnel window edge
07/29/2003US6600187 Semiconductor memory device and method for manufacturing the same
07/29/2003US6600186 Process technology architecture of embedded DRAM
07/29/2003US6600185 Chemical mechanical polishing; protection against etching damage; prevents repeat annealing
07/29/2003US6600183 Integrated circuit capacitor and memory
07/29/2003US6600181 Semiconductor integrated circuit and designing method thereof
07/29/2003US6600180 Semiconductor device, method of manufacturing the same and exposure mask for implantation
07/29/2003US6600178 Heterojunction bipolar transistor
07/29/2003US6600176 Semiconductor device with protective element
07/29/2003US6600174 Light receiving element and semiconductor laser device
07/29/2003US6600173 Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
07/29/2003US6600171 Semiconductor component and system for fabricating contacts on semiconductor components
07/29/2003US6600170 CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
07/29/2003US6600166 Scanning exposure method
07/29/2003US6600163 In-process wafer charge monitor and control system for ion implanter
07/29/2003US6600162 Method and device for exposing a substrate to light
07/29/2003US6600138 Rapid thermal processing system for integrated circuits
07/29/2003US6600006 Polyamic ester prepared by partially substituting hydrogen atoms of carboxylic groups of a polyamic acid with acid labile groups, the polyamic ester comprising one or more repeating units represented by Formula 1, and each of at least one
07/29/2003US6599951 Antireflective porogens
07/29/2003US6599870 In aqueous solution containing amine
07/29/2003US6599847 Sandwich composite dielectric layer yielding improved integrated circuit device reliability
07/29/2003US6599846 Method of forming a silica-containing coating film with a low dielectric constant and semiconductor substrate coated with such a film
07/29/2003US6599845 Oxidizing method and oxidation system
07/29/2003US6599844 Overcoating with photoresist patterns
07/29/2003US6599843 In-situ mask technique for producing III-V semiconductor components
07/29/2003US6599842 Method for rounding corners and removing damaged outer surfaces of a trench
07/29/2003US6599841 Method for manufacturing a semiconductor device
07/29/2003US6599840 Material removal method for forming a structure
07/29/2003US6599839 Plasma etch process for nonhomogenous film
07/29/2003US6599838 Method for forming metal filled semiconductor features to improve a subsequent metal CMP process
07/29/2003US6599837 Chemical mechanical polishing composition and method of polishing metal layers using same
07/29/2003US6599836 Planarizing solutions, planarizing machines and methods for mechanical or chemical-mechanical planarization of microelectronic-device substrate assemblies
07/29/2003US6599834 Process of manufacturing a semiconductor device with an electroplated wiring layer
07/29/2003US6599833 Method and article for filling apertures in a high performance electronic substrate
07/29/2003US6599832 Silicide pattern structures and methods of fabricating the same
07/29/2003US6599831 Metal gate electrode using silicidation and method of formation thereof
07/29/2003US6599830 Semiconductor device and manufacturing method thereof
07/29/2003US6599829 Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization
07/29/2003US6599828 Copper reflow process
07/29/2003US6599827 Methods of forming capped copper interconnects with improved electromigration resistance
07/29/2003US6599826 Method for fabricating a low dielectric constant material layer
07/29/2003US6599825 Method for forming wiring in semiconductor device
07/29/2003US6599824 System for and method of forming local interconnect using microcontact printing
07/29/2003US6599823 Method for improving package bonding between multi-level interconnection lines and low K inter-metal dielectric
07/29/2003US6599821 Method for fabricating conductive line pattern for semiconductor device
07/29/2003US6599820 Method of producing a semiconductor device
07/29/2003US6599819 Semiconductor device with source/drain regions of high impurity concentration and its manufacture
07/29/2003US6599818 Semiconductor device manufacturing method, heat treatment apparatus, and heat treatment method
07/29/2003US6599817 Semiconductor constructions, and methods of forming semiconductor constructions
07/29/2003US6599816 Method of manufacturing silicon epitaxial wafer
07/29/2003US6599815 Method and apparatus for forming a silicon wafer with a denuded zone
07/29/2003US6599814 Method for removal of sic
07/29/2003US6599813 Method of forming shallow trench isolation for thin silicon-on-insulator substrates
07/29/2003US6599812 Manufacturing method for a thick oxide layer
07/29/2003US6599811 Semiconductor device having a shallow isolation trench
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