Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2004
05/06/2004WO2004038275A1 Microfabrication tool pedestal and method of use
05/06/2004WO2004038072A2 Plating uniformity control by contact ring shaping
05/06/2004WO2004038065A1 Stabilized aluminum laminate having aluminum and stabilizing layer laminated thereon
05/06/2004WO2004037962A2 Aqueous phosphoric acid compositions for cleaning semiconductor devices
05/06/2004WO2004037937A1 A corrosion retarding polishing slurry for the chemical mechanical polishing of copper surfaces
05/06/2004WO2004037878A2 Co-curable compositions
05/06/2004WO2004037877A2 Organosiloxanes
05/06/2004WO2004037866A2 Photoresists containing sulfonamide component
05/06/2004WO2004037711A2 Processes for hermetically packaging wafer level microscopic structures
05/06/2004WO2004037490A1 Transparent microporous materials for cmp
05/06/2004WO2004037452A1 Equipment and method for washing parts
05/06/2004WO2004025712A3 Method for p-type doping wide band gap oxide semiconductors
05/06/2004WO2004017423A3 Sensor arrangement
05/06/2004WO2004017378A3 Atomic layer deposition of high k metal silicates
05/06/2004WO2004010485A3 Semiconductor element with stress-carrying semiconductor layer and corresponding production method
05/06/2004WO2004010458A3 Plasma implantation system and method with target movement
05/06/2004WO2004006140A3 Method and apparatus for automatic sensor installation
05/06/2004WO2003100826A3 Lithography laser with beam delivery and beam pointing control
05/06/2004WO2003090347A3 Acoustic wave sensor apparatus, method and system using wide bandgap materials
05/06/2004WO2003063239A3 Method and apparatus for controlling die attach fillet height to reduce die shear stress
05/06/2004WO2003054256B1 Method and device for depositing crystalline layers on crystalline substrates
05/06/2004WO2003017479A3 Electronic device and method of testing and of manufacturing
05/06/2004WO2002073699A9 Nanofabrication
05/06/2004WO2002048432A9 Method for patterning metal using nanoparticle containing precursors
05/06/2004WO2002004711A3 Method and associated apparatus for tilting a substrate upon entry for metal deposition
05/06/2004US20040088675 Method of and computer program product for designing patterns, and method of manufacturing semiconductor device
05/06/2004US20040088672 Architecture and interconnect scheme for programmable logic circuits
05/06/2004US20040088667 Semiconductor integrated circuit capable of facilitating layout modification
05/06/2004US20040088659 Semiconductor device having scan flip-flop and design method therefor
05/06/2004US20040088658 Method of designing semiconductor device
05/06/2004US20040088471 Equi-potential sensing magnetic random access memory (MRAM) with series diodes
05/06/2004US20040088416 Printed circuit board and method manufacturing the same
05/06/2004US20040088071 Aligner evaluation system, aligner evaluation method, a computer program product, and a method for manufacturing a semiconductor device
05/06/2004US20040088068 Method and apparatus for providing first-principles feed-forward manufacturing control
05/06/2004US20040087694 Positive type resist composition
05/06/2004US20040087681 Toughened epoxy-anhydride no-flow underfill encapsulant
05/06/2004US20040087456 enables damage-free, residue-free cleaning of substrates having particulate contamination on Si/SiO2 substrates
05/06/2004US20040087263 Semiconductor wafer handler
05/06/2004US20040087262 Polishing silicon wafers
05/06/2004US20040087258 Polishing method and apparatus
05/06/2004US20040087257 CMP equipment for use in planarizing a semiconductor wafer
05/06/2004US20040087254 Fluid-pressure regulated wafer polishing head
05/06/2004US20040087251 Semiconductor processing methods of removing conductive material
05/06/2004US20040087250 Method and apparatus for forming and using planarizing pads for mechanical and chemical-mechanical planarization of microelectronic substrates
05/06/2004US20040087249 Alignment mark and exposure alignment system and method using the same
05/06/2004US20040087248 Polishing method and apparatus
05/06/2004US20040087187 Recipe cascading in a wafer processing system
05/06/2004US20040087186 Using sonic energy in connection with laser-assisted direct imprinting
05/06/2004US20040087185 Heat treatment method and heat treatment system
05/06/2004US20040087184 Ionic additives for extreme low dielectric constant chemical formulations
05/06/2004US20040087183 Selectively growing a polymeric material on a semiconductor substrate
05/06/2004US20040087182 Method for synthesizing polymeric material, method for forming polymer thin film and method for forming interlayer insulating film
05/06/2004US20040087180 Oxide film forming method
05/06/2004US20040087179 Method for forming integrated dielectric layers
05/06/2004US20040087178 Method for manufacturing semiconductor device
05/06/2004US20040087177 Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same
05/06/2004US20040087176 Forming a self-aligned pattern on an existing pattern on a substrate by coating a masking material to the substrate and allowing a portion of the masking material to preferentially attach to portions of the existing pattern; including metal elements and dielectrics; microelectronics; simplifification
05/06/2004US20040087175 Application of impressed-current cathodic protection to prevent metal corrosion and oxidation
05/06/2004US20040087174 Supercritical carbon dioxide/chemical formulation for ashed and unashed aluminum post-etch residue removal
05/06/2004US20040087171 Combined conformal/non-conformal seed layers for metallic interconnects
05/06/2004US20040087169 Dry etching method and semiconductor device manufacturing method
05/06/2004US20040087168 Method and apparatus for supporting a semiconductor wafer during processing
05/06/2004US20040087167 Method for removing polymeric residue contamination on semiconductor feature sidewalls
05/06/2004US20040087166 Method for making a dual damascene interconnect using a dual hard mask
05/06/2004US20040087164 Scum solution for chemically amplified resist patterning in cu/low k dual damascene
05/06/2004US20040087163 Method for forming magnetic clad bit line
05/06/2004US20040087161 Code implantation process
05/06/2004US20040087160 Method and structure for controlling the interface roughness of cobalt disilicide
05/06/2004US20040087159 Method for manufacturing multi-thickness gate dielectric layer of semiconductor device
05/06/2004US20040087158 Substrate processing method and substrate processing apparatus
05/06/2004US20040087156 Method of manufacturing semiconductor device
05/06/2004US20040087155 Method of removing sidewall spacers in the fabrication of a semiconductor device using an improved removal process
05/06/2004US20040087154 System architecture of semiconductor manufacturing equipment
05/06/2004US20040087153 Method of etching a silicon-containing dielectric material
05/06/2004US20040087150 Structural element and process for its production
05/06/2004US20040087149 Method for reducing contamination, copper reduction, and depositing a dielectric layer on a semiconductor device
05/06/2004US20040087148 Copper interconnect by immersion/electroless plating in dual damascene process
05/06/2004US20040087147 Fast ramp anneal for hillock suppression in copper-containing structures
05/06/2004US20040087146 Method of preparing whole semiconductor wafer for analysis
05/06/2004US20040087145 Semiconductor device and method of manufacturing
05/06/2004US20040087144 Cobalt silicide formation method employing wet chemical silicon substrate oxidation
05/06/2004US20040087143 Process for atomic layer deposition of metal films
05/06/2004US20040087142 Method for electroless plating a contact pad
05/06/2004US20040087141 Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
05/06/2004US20040087140 Process for fabricating an electrical circuit comprising a polishing step
05/06/2004US20040087139 Nitrogen-free antireflective coating for use with photolithographic patterning
05/06/2004US20040087138 Method for manufacturing buried wiring structure
05/06/2004US20040087137 Method of manufacturing interconnection structure applied to semiconductor device
05/06/2004US20040087136 Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure
05/06/2004US20040087135 Very low effective dielectric constant interconnect Structures and methods for fabricating the same
05/06/2004US20040087134 Method for writing to the magnetoresistive memory cells of an integrated magnetoresistive semiconductor memory
05/06/2004US20040087133 Method for manufacturing semiconductor device having porous structure with air-gaps
05/06/2004US20040087131 Method for the solder-stop structuring of elevations on wafers
05/06/2004US20040087130 Semiconductor device and mounted semiconductor device structure
05/06/2004US20040087129 Solder bump structure and laser repair process for memory device
05/06/2004US20040087128 Method and materials for printing particle-enhanced electrical contacts
05/06/2004US20040087127 Process and arrangement for the selective metallization of 3D structures
05/06/2004US20040087126 Method of forming a through-substrate interconnect
05/06/2004US20040087125 Method for manufacturing semiconductor device
05/06/2004US20040087124 Method for fabricating semiconductor device