Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2004
05/13/2004US20040091820 Cleaning after doping or etching without leaving residue; decomposing photosensitizer with light exposure prior to nonaqueous solvent treatment
05/13/2004US20040091819 Suppressing short circuiting; lower cost
05/13/2004US20040091797 Correcting design data of layout pattern; calculating area ratio and density; positional accuracy
05/13/2004US20040091796 Pellicle for lithography, and a method for producing it
05/13/2004US20040091795 Rapid, error free semiconductor batch production
05/13/2004US20040091794 Phase edge phase shift mask enforcing a width of a field gate image and fabrication method thereof
05/13/2004US20040091793 Faster wafer fabrication without wasting exposure area; simultaneous evaluation
05/13/2004US20040091792 Photoresist patterning variety of sizes and pitches; simple, easy fabrication
05/13/2004US20040091717 Nitrogen-free fluorine-doped silicate glass
05/13/2004US20040091710 For use in display devices, information storage, biological tagging materials, photovoltaics, sensors and catalysts
05/13/2004US20040091697 For connecting fine-pitched terminals, for example, in case of electrically connecting input terminals of liquid crystal panels (liquid crystal displays) to outer leads in TAB (Tape Automated Bonding)
05/13/2004US20040091636 Feeding a raw material gas containing a halogen into an inlet vessel having a perforated plate made of metal; converting the raw material gas into a plasma to generate a raw material gas plasma; etching the perforated plate; passing the precursor
05/13/2004US20040091634 Passivated magneto-resistive bit structure and passivation method therefor
05/13/2004US20040091625 Methods of filling a feature on a substrate with copper nanocrystals
05/13/2004US20040091623 Organic anti-reflective coating polymers, anti-reflective coating composition comprising the same and preparation methods thereof
05/13/2004US20040091618 For forming a photoresist film having a uniform thickness without damaging substrate and without a need for a without need for a large amount of photoresist and without need for removing an unnecessary photoresist from an edge of substrate
05/13/2004US20040091607 Method for forming a liquid film on a substrate
05/13/2004US20040091606 Dropping a liquid adjusted to be spread into a give amount on a substrate to be processed from a dropping nozzle or dropping nozzles of a dropping unit onto the substrate, and then moving the dropping unit and substrate
05/13/2004US20040091419 Zeolite sol and method for preparing the same, composition for forming porous film, porous film and method for forming the same, interlevel insulator film, and semiconductor device
05/13/2004US20040091349 Methods for transporting wafers for vacuum processing
05/13/2004US20040091343 Method and device for changing a semiconductor wafer position
05/13/2004US20040091342 Semiconductor chip pickup device
05/13/2004US20040091338 Transfer system and apparatus for workpiece containers and method of transferring the workpiece containers using the same
05/13/2004US20040091337 Foup loading apparatus for foup opener
05/13/2004US20040091142 Qualifying patterns, patterning processes, or patterning apparatus in the fabrication of microlithographic patterns
05/13/2004US20040091141 Automatic accurate alignment method for a semiconductor wafer cutting apparatus
05/13/2004US20040090856 Thin film magnetic memory device for programming required information with an element similar to a memory cell and information programming method
05/13/2004US20040090844 Multi-bit magnetic memory cells
05/13/2004US20040090843 Large line conductive pads for interconnection of stackable circuitry
05/13/2004US20040090842 Magneto resistive storage device having a magnetic field sink layer
05/13/2004US20040090841 Triple sample sensing for magnetic random access memory (MRAM) with series diodes
05/13/2004US20040090838 Semiconductor integrated circuit device
05/13/2004US20040090835 Magentic memory and method for optimizing write current a in magnetic memory
05/13/2004US20040090829 Memory card and its manufacturing method
05/13/2004US20040090822 MRAM and methods for manufacturing and driving the same
05/13/2004US20040090816 6f2 3-transistor dram gain cell
05/13/2004US20040090815 Nonvolatile variable resistor, memory device, and scaling method of nonvolatile variable resistor
05/13/2004US20040090813 DRAM cell structure capable of high integration and fabrication method thereof
05/13/2004US20040090810 Ferroelectric memory
05/13/2004US20040090809 Memory device array having a pair of magnetic bits sharing a common conductor line
05/13/2004US20040090756 Chip packaging structure and manufacturing process thereof
05/13/2004US20040090734 Stack-film trench capacitor and method for manufacturing the same
05/13/2004US20040090733 Single layer capacitor
05/13/2004US20040090732 Plated terminations
05/13/2004US20040090639 Method and apparatus for quantitative quality inspection of substrate such as wafer
05/13/2004US20040090617 Method for optimising the image properties of at least two optical elements as well as methods for optimising the image properties of at least three optical elements
05/13/2004US20040090609 Illumination system and exposure apparatus and method
05/13/2004US20040090608 Illumination optical apparatus and exposure apparatus
05/13/2004US20040090605 Advanced mask cleaning and handling
05/13/2004US20040090282 Transmission line and semiconductor device
05/13/2004US20040090223 Mechanism for fixing probe card
05/13/2004US20040090152 Method and apparatus for implementing measurement or instrumentation on production equipment
05/13/2004US20040090129 Positioning apparatus and charged-particle-beam exposure apparatus
05/13/2004US20040089958 Conductor wafer and substrate
05/13/2004US20040089956 Chip is attached to a baseplate, a conductive layer that is at least as high as the chip is attached to the baseplate. A cover plate, provided with electrically conductive surfaces, is arranged on this conductive layer, which is both
05/13/2004US20040089955 A first integrated circuit affixed to a substrate; an electronic circuit component affixed to the substrate; a first encapsulation structure encasing the first integrated circuit; a second integrated circuit affixed to the first
05/13/2004US20040089953 Via construction
05/13/2004US20040089951 Post passivation interconnection schemes on top of the IC chips
05/13/2004US20040089950 Semiconductor device with dummy structure
05/13/2004US20040089948 Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer
05/13/2004US20040089947 Semiconductor device with multilayer conductive structure formed on a semiconductor substrate
05/13/2004US20040089938 Bonding pad design
05/13/2004US20040089935 Electronic component having a semiconductor chip and method for populating a circuit carrier during the production of the electronic component
05/13/2004US20040089929 Semiconductor package structure and method for manufacturing the same
05/13/2004US20040089928 Mold resin-sealed power semiconductor device having insulating resin layer fixed on bottom surface of heat sink and metal layer on the resin layer
05/13/2004US20040089924 Electronic device and method for fabricating the same
05/13/2004US20040089922 Semiconductor device and method therefor
05/13/2004US20040089921 Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same
05/13/2004US20040089920 Stacked memory cell and process of fabricating same
05/13/2004US20040089919 Single crystal GaN substrate, method of growing same and method of producing same
05/13/2004US20040089918 Bipolar transistor device having phosphorous
05/13/2004US20040089917 Three-dimensional memory array and method of fabrication
05/13/2004US20040089915 Semiconductor device with fuses
05/13/2004US20040089914 Isolation techniques for reducing dark current in CMOS image sensors
05/13/2004US20040089913 Semiconductor memory device with efficiently laid-out internal interconnection lines
05/13/2004US20040089912 Semiconductor device
05/13/2004US20040089911 Semiconductor integrated circuit and method of manufacturing the same
05/13/2004US20040089904 Mram with asymmetric cladded conductor
05/13/2004US20040089902 Semiconductor device and method for manufacturing the same
05/13/2004US20040089901 Semiconductor integrated circuit and semiconductor substrate of the same
05/13/2004US20040089900 Method of pattering thin film and tft array substrate using it and production method therefor
05/13/2004US20040089899 Semiconductor device formed on silicon-on-insulator substrate
05/13/2004US20040089894 Semiconductor device and method of manufacturing the same
05/13/2004US20040089893 Annular gate and technique for fabricating an annular gate
05/13/2004US20040089892 Trench Gate Type Field Effect Transistor and Method of Manufacture Thereof
05/13/2004US20040089891 Semiconductor device including electrode or the like having opening closed and method of manufacturing the same
05/13/2004US20040089890 One transistor DRAM cell structure and method for forming
05/13/2004US20040089889 Magnetic memory device having soft reference layer
05/13/2004US20040089888 A ferromagnetic data layer of a magnetic memory element is formed with a controlled nucleation site. A Magnetic Random Access Memory ("MRAM") device may include an array of such magnetic memory elements.
05/13/2004US20040089887 A new relatively high-k gate dielectric gate material comprising calcium oxide will reduce leakage from the silicon substrate to the polysilicon gate, prevent boron penetration in p-channel devices, and reduce electron trapping in the
05/13/2004US20040089886 Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same
05/13/2004US20040089884 Thin film transistor array panel and method for fabricating the same
05/13/2004US20040089883 CMOS image sensor and method of fabricating the same
05/13/2004US20040089881 Semiconductor substrate defining a plurality of rows, each row including areas for a sequence of cells; a plurality of active regions disposed in each of the rows constituting semiconductor elements of associated cells; and a wiring
05/13/2004US20040089880 Methods for providing an integrated circuit package with an alignment mechanism
05/13/2004US20040089878 Thin-film transistor, panel, and methods for producing them
05/13/2004US20040089876 Semiconductor photodetector and avalanche photodiode
05/13/2004US20040089875 Heterojunction bipolar transistor
05/13/2004US20040089863 Method of forming silicon-on-insulator comprising integrated circuitry
05/13/2004US20040089862 Thin-film transistor, switching circuit, active element substrate, electro-optical device, electronic apparatus, thermal head, droplet ejecting head, printer, and thin-film-transistor driving and light-emitting display device